feat(adapter-riscv): add RiscVPlatform, PLIC driver, and kernel boot on QEMU

crates/adapter-riscv/src/platform.rs

@@ -0,0 +1,77 @@
+use domain::memory::MemoryRegion;
+use domain::thread::SavedContext;
+use platform::Platform;
+use types::{
+    address::{EntryPoint, PhysicalAddress, StackPointer},
+    bounded::PageCount,
+    id::{CoreId, IrqId, ProcessId},
+    permission::PermissionSet,
+    time::{Ticks, TimerDuration},
+};
+
+use crate::plic::Plic;
+use crate::timer;
+
+pub struct RiscVPlatform {
+    num_cores: u8,
+}
+
+impl RiscVPlatform {
+    pub fn new() -> Self {
+        Self { num_cores: 1 }
+    }
+}
+
+impl Platform for RiscVPlatform {
+    fn configure_protection(&mut self, _process: ProcessId, _regions: &[MemoryRegion]) {
+        // page table activation happens separately per context switch
+    }
+
+    fn context_switch(&mut self, _from: &mut SavedContext, _to: &SavedContext) {
+        // context switch is handled by the trap vector assembly
+    }
+
+    fn enable_user_mode(&mut self, _entry: EntryPoint, _stack: StackPointer) -> ! {
+        // handled by setting up TrapFrame and sret in the main loop
+        loop { unsafe { core::arch::asm!("wfi") }; }
+    }
+
+    fn set_timer(&mut self, _duration: TimerDuration) {
+        let now = timer::read_time();
+        timer::set_next_timer(now + 10_000_000);
+    }
+
+    fn current_ticks(&self) -> Ticks {
+        Ticks::from_raw(timer::read_time())
+    }
+
+    fn mask_irq(&mut self, irq: IrqId) {
+        Plic::disable(irq.raw() as u32);
+    }
+
+    fn unmask_irq(&mut self, irq: IrqId) {
+        Plic::enable(irq.raw() as u32);
+    }
+
+    fn send_ipi(&mut self, _target: CoreId) {
+        // single core — no-op
+    }
+
+    fn core_id(&self) -> CoreId {
+        CoreId::from_raw(0)
+    }
+
+    fn num_cores(&self) -> u8 {
+        self.num_cores
+    }
+
+    fn map_shared(
+        &mut self,
+        _process: ProcessId,
+        _base: PhysicalAddress,
+        _size: PageCount,
+        _permissions: PermissionSet,
+    ) {
+        // page table mapping for shared memory — deferred to full MMU integration
+    }
+}