feat: wire display + input servers to snake, fix QEMU 11.x GPU bug
VirtIO GPU: QEMU 11.x has RESOURCE_ATTACH_BACKING (0x0104) and RESOURCE_FLUSH (0x0106) command types swapped in its legacy MMIO VirtIO GPU implementation. Workaround: send swapped type values. Confirmed via QEMU monitor (xp shows correct bytes in memory) and QEMU trace events (device dispatches to wrong handler). Display pipeline now works end-to-end: adapter → GPU init → create_2d → attach_backing → set_scanout display-server → clear(blue) → flush → transfer + resource_flush snake → draw commands via IPC → display renders → flush to GPU Input server: - New driver-input-uart crate (reads UART at mapped VA 0x20000) - New bins/input-qemu composition root - Adapter loads input-server, maps UART MMIO into its address space - Init delegates both display_ep (slot 0) and input_ep (slot 1) to snake - WASD keys → UART → input-server → IPC → snake direction change Snake game runs with display and input, exits on wall collision.
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@@ -1,6 +1,7 @@
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use crate::hw::uart::Uart;
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use crate::hw::virtio_gpu::VirtioGpu;
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use crate::{kernel_ref, mmu};
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use types::display::Dimension;
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use types::id::ProcessId;
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const GPU_VA: usize = 0x20000;
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@@ -8,8 +9,8 @@ const VQUEUE_VA: usize = 0x21000;
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const CMDBUF_VA: usize = 0x23000;
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const PHYSINFO_VA: usize = 0x24000;
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const FB_VA: usize = 0x100000;
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const FB_WIDTH: types::display::Dimension = types::display::Dimension::new(640);
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const FB_HEIGHT: types::display::Dimension = types::display::Dimension::new(480);
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const FB_WIDTH: Dimension = Dimension::new(640);
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const FB_HEIGHT: Dimension = Dimension::new(480);
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const FB_BPP: usize = 4;
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const FB_PAGES: usize = (FB_WIDTH.raw() as usize * FB_HEIGHT.raw() as usize * FB_BPP + 4095) / 4096;
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@@ -48,10 +49,155 @@ pub fn configure(uart: &Uart, display_pid: ProcessId) {
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}
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gpu.init_device(vq_phys);
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gpu.setup_framebuffer(cmd_phys, vq_phys, fb_phys, FB_WIDTH, FB_HEIGHT);
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// Raw GPU setup — bypass hw-virtio to debug
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let w = FB_WIDTH.raw() as u32;
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let h = FB_HEIGHT.raw() as u32;
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let fb_size = w * h * 4;
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// Use separate command pages for each command
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let cmd1 = mmu::allocator::alloc_zeroed_page();
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let cmd2 = mmu::allocator::alloc_zeroed_page();
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let cmd3 = mmu::allocator::alloc_zeroed_page();
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// CMD 1: RESOURCE_CREATE_2D
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raw_gpu_cmd(uart, vq_phys, cmd1, |p| unsafe {
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core::ptr::write_volatile(p.add(0) as *mut u32, 0x0101); // type
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core::ptr::write_volatile(p.add(24) as *mut u32, 1); // resource_id
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core::ptr::write_volatile(p.add(28) as *mut u32, 1); // format B8G8R8A8
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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}, 40, "create_2d");
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// CMD 2: RESOURCE_ATTACH_BACKING (type swapped due to QEMU 11.x bug)
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raw_gpu_cmd(uart, vq_phys, cmd2, |p| unsafe {
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core::ptr::write_volatile(p.add(0) as *mut u32, 0x0106);
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core::ptr::write_volatile(p.add(24) as *mut u32, 1); // resource_id
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core::ptr::write_volatile(p.add(28) as *mut u32, 1); // nr_entries
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core::ptr::write_volatile(p.add(32) as *mut u64, fb_phys as u64);
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core::ptr::write_volatile(p.add(40) as *mut u32, fb_size);
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}, 48, "attach");
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// CMD 3: SET_SCANOUT
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raw_gpu_cmd(uart, vq_phys, cmd3, |p| unsafe {
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core::ptr::write_volatile(p.add(0) as *mut u32, 0x0103); // type
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core::ptr::write_volatile(p.add(24) as *mut u32, 0); // rect.x
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core::ptr::write_volatile(p.add(28) as *mut u32, 0); // rect.y
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core::ptr::write_volatile(p.add(32) as *mut u32, w); // rect.width
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core::ptr::write_volatile(p.add(36) as *mut u32, h); // rect.height
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core::ptr::write_volatile(p.add(40) as *mut u32, 0); // scanout_id
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core::ptr::write_volatile(p.add(44) as *mut u32, 1); // resource_id
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}, 48, "scanout");
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// Fill framebuffer with blue
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let fb = fb_phys as *mut u32;
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let total = w as usize * h as usize;
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for i in 0..total {
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unsafe { core::ptr::write_volatile(fb.add(i), 0xFF4040FF); }
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}
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// Transfer + flush using shared cmd buffer
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raw_gpu_cmd(uart, vq_phys, cmd_phys, |p| unsafe {
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core::ptr::write_volatile(p.add(0) as *mut u32, 0x0105); // TRANSFER_TO_HOST_2D
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core::ptr::write_volatile(p.add(24) as *mut u32, 0); // rect.x
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core::ptr::write_volatile(p.add(28) as *mut u32, 0); // rect.y
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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core::ptr::write_volatile(p.add(40) as *mut u64, 0); // offset
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core::ptr::write_volatile(p.add(48) as *mut u32, 1); // resource_id
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}, 56, "xfer");
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raw_gpu_cmd(uart, vq_phys, cmd_phys, |p| unsafe {
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core::ptr::write_volatile(p.add(0) as *mut u32, 0x0104); // RESOURCE_FLUSH (swapped for QEMU 11.x)
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core::ptr::write_volatile(p.add(24) as *mut u32, 0);
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core::ptr::write_volatile(p.add(28) as *mut u32, 0);
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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core::ptr::write_volatile(p.add(40) as *mut u32, 1); // resource_id
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}, 48, "flush");
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uart.write_str("k-os: VirtIO GPU configured\n");
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}
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fn raw_gpu_cmd(uart: &Uart, vq_phys: usize, cmd_phys: usize, write_fn: impl FnOnce(*mut u8), cmd_len: u32, label: &str) {
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let resp_phys = cmd_phys + 512;
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// Zero cmd + response area
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unsafe {
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core::ptr::write_bytes(cmd_phys as *mut u8, 0, 1024);
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}
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// Write command
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write_fn(cmd_phys as *mut u8);
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// Verify type field
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let cmd_type = unsafe { core::ptr::read_volatile(cmd_phys as *const u32) };
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unsafe {
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let desc = vq_phys as *mut u8;
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// Desc 0: cmd (readable)
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core::ptr::write_volatile(desc as *mut u64, cmd_phys as u64);
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core::ptr::write_volatile(desc.add(8) as *mut u32, cmd_len);
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core::ptr::write_volatile(desc.add(12) as *mut u16, 1); // NEXT
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core::ptr::write_volatile(desc.add(14) as *mut u16, 1);
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// Desc 1: response (writable)
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let desc1 = desc.add(16);
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core::ptr::write_volatile(desc1 as *mut u64, resp_phys as u64);
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core::ptr::write_volatile(desc1.add(8) as *mut u32, 24);
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core::ptr::write_volatile(desc1.add(12) as *mut u16, 2); // WRITE
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core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
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let avail = vq_phys + 128; // 8 descs * 16 bytes
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let idx = core::ptr::read_volatile((avail + 2) as *const u16);
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core::ptr::write_volatile((avail + 4 + (idx as usize % 8) * 2) as *mut u16, 0);
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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core::ptr::write_volatile((avail + 2) as *mut u16, idx.wrapping_add(1));
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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let gpu_mmio = hw_virtio::mmio::DirectMmio::new(
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crate::hw::virtio_gpu::VirtioGpu::probe().unwrap().base()
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);
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// Dump desc chain for this command
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let d0_addr = core::ptr::read_volatile(desc as *const u64);
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let d0_len = core::ptr::read_volatile(desc.add(8) as *const u32);
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let d0_flags = core::ptr::read_volatile(desc.add(12) as *const u16);
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let cmd_byte0 = core::ptr::read_volatile(d0_addr as *const u32);
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uart.write_str("k-os: desc0 addr=");
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uart.write_hex(d0_addr as usize);
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uart.write_str(" len=");
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uart.write_dec(d0_len as usize);
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uart.write_str(" cmd[0]=");
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uart.write_hex(cmd_byte0 as usize);
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uart.put_char(b'\n');
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use hw_virtio::mmio::MmioAccess;
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gpu_mmio.write(0x050, 0);
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let used = vq_phys + 4096;
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let expected = idx.wrapping_add(1);
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let mut timeout = 10_000_000u32;
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while core::ptr::read_volatile((used + 2) as *const u16) != expected {
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core::hint::spin_loop();
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timeout -= 1;
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if timeout == 0 {
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uart.write_str("k-os: ");
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uart.write_str(label);
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uart.write_str(" TIMEOUT\n");
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return;
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}
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}
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let resp = core::ptr::read_volatile(resp_phys as *const u32);
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uart.write_str("k-os: ");
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uart.write_str(label);
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uart.write_str(" type=");
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uart.write_hex(cmd_type as usize);
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uart.write_str(" resp=");
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uart.write_hex(resp as usize);
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uart.put_char(b'\n');
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}
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}
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fn map_page(pt: &mut mmu::PageTable, va: usize, pa: usize) {
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mmu::map(pt, mmu::Mapping {
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va: types::address::VirtualAddress::from_raw(va),
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19
crates/adapter-riscv/src/devices/input_setup.rs
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19
crates/adapter-riscv/src/devices/input_setup.rs
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@@ -0,0 +1,19 @@
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use crate::hw::uart::Uart;
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use crate::{board, kernel_ref, mmu};
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use types::id::ProcessId;
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const UART_VA: usize = 0x20000;
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pub fn configure(uart: &Uart, input_pid: ProcessId) {
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let pt_addr = kernel_ref().platform_mut().page_table_for(input_pid);
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let pt = unsafe { &mut *(pt_addr as *mut mmu::PageTable) };
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mmu::map(pt, mmu::Mapping {
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va: types::address::VirtualAddress::from_raw(UART_VA),
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pa: types::address::PhysicalAddress::from_raw(board::UART_BASE),
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pages: 1,
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flags: mmu::Sv39Flags::user_rw(),
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});
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uart.write_str("k-os: UART mapped for input\n");
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}
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@@ -1,2 +1,3 @@
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pub mod gpu_setup;
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pub mod input_setup;
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pub mod storage_setup;
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