perf(kernel): linked cap tree, translate-based page lookup, next-fit frames/heap, targeted dequeue; host benches

crates/adapter-riscv/src/mmu/mod.rs

@@ -4,7 +4,7 @@ pub mod page_table;
 pub use allocator::init_allocator;
 pub use page_table::{
     PAGE_SIZE, PageTable, Sv39Flags, USER_VA_END, USER_VA_START, activate, active_root, check_wx,
-    create_user_root, init_kernel_page_table, map_user_page, unmap_user_page,
+    create_user_root, init_kernel_page_table, map_user_page, translate_user, unmap_user_page,
 };
 
 /// The kernel lives in the upper half of the address space: all of RAM and

crates/adapter-riscv/src/mmu/page_table.rs

@@ -405,6 +405,16 @@ pub fn map_user_page(
     Ok(())
 }
 
+/// The physical page `va` maps to in the address space at `root_pa`.
+pub fn translate_user(root_pa: usize, va: usize) -> Option<usize> {
+    if !in_user_window(va) {
+        return None;
+    }
+    let l0 = user_leaf_table(root_pa, va, None).ok()?;
+    let entry = l0.entries[vpn(va, 0)];
+    entry.is_valid().then(|| (entry.ppn() << 12) as usize)
+}
+
 pub fn unmap_user_page(root_pa: usize, va: usize) {
     if !in_user_window(va) {
         return;

crates/adapter-riscv/src/platform.rs

@@ -103,6 +103,11 @@ impl Platform for RiscVPlatform {
         }
     }
 
+    fn translate(&self, process: ProcessId, va: VirtualAddress) -> Option<PhysicalAddress> {
+        let root = self.root(process)?;
+        mmu::translate_user(root, va.raw()).map(PhysicalAddress::from_raw)
+    }
+
     fn zero_frame(&mut self, pa: PhysicalAddress) {
         // SAFETY: pool frames are RAM, mapped at `phys_to_virt`, and the
         // kernel only zeroes frames it has just allocated.