perf(kernel): linked cap tree, translate-based page lookup, next-fit frames/heap, targeted dequeue; host benches

crates/adapter-riscv/src/platform.rs

@@ -103,6 +103,11 @@ impl Platform for RiscVPlatform {
         }
     }
 
+    fn translate(&self, process: ProcessId, va: VirtualAddress) -> Option<PhysicalAddress> {
+        let root = self.root(process)?;
+        mmu::translate_user(root, va.raw()).map(PhysicalAddress::from_raw)
+    }
+
     fn zero_frame(&mut self, pa: PhysicalAddress) {
         // SAFETY: pool frames are RAM, mapped at `phys_to_virt`, and the
         // kernel only zeroes frames it has just allocated.