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feat: SMP stage 1 (4 harts, per-hart guarded stacks, home-core affinity, IPIs, TLB shootdown, one temporary kernel lock), 4-core storm

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Gabriel Kaszewski
2026-10-27 00:56:15 +01:00
parent b87a62475f
commit 2e665fd66e
22 changed files with 995 additions and 230 deletions
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7
docs/ADAPTERS.md
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@@ -21,9 +21,10 @@ This generates `crates/adapter-<arch>/` with the standard structure. Then:
the final kernel table may be mapped in the lower half.
Keep text, read-only data and writable data on separate pages and
export their page-aligned boundaries (`_text_start`, `_text_end`,
`_rodata_end`, `_stack_guard`, `_stack_bottom`): the kernel maps each
range with only the access it needs (W^X) and leaves a guard page under
the stack.
`_rodata_end`, `_stacks_start`, `_stacks_end`): the kernel maps each
range with only the access it needs (W^X). The stacks area holds one
slot per hart, a guard page (left unmapped) then that hart's kernel
stack; the boot stub picks the slot from the hart id.
5. Implement the TODOs in `hw/`, `mmu/`, `trap/`, and `platform.rs`
## Structure