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feat: proper IPC-based boot — init loads servers from storage via IPC, VirtIO GPU driver

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Complete microkernel boot pipeline: adapter loads only init + storage + display
from disk. Init bootstraps all other servers by reading binaries from the
storage server via IPC, parsing ELF, creating processes, mapping pages, and
spawning threads.

New syscalls:
- CreateEndpoint: userspace endpoint creation with full capability grant
- DebugPutchar: debug output to UART from userspace
- MapPage: cross-process page mapping (init loads binaries into children)
- SpawnThreadIn: spawn thread in another process via capability

Key fixes:
- Per-process L1 page tables for VPN[2]=0 (prevents cross-process corruption)
- Separate kernel_pt from page_tables[0] (init pid=0 overwrote kernel PT ref)
- Thread Running state set in switch_to_next (syscalls rejected without it)
- Pending IPC results applied during context switch
- SIE disabled during boot (timer can't preempt into unready processes)
- User heap VA starts at 0x40000 (avoids shared buffer at 0x30000)
- RequestPages maps at user VAs via per-process heap allocator

VirtIO GPU:
- Adapter probes for GPU device, initializes resource/scanout/backing
- Display server writes to mapped framebuffer, flushes via GPU virtqueue
- 640x480 BGRA framebuffer with transfer-to-host and resource-flush

Storage server:
- Userspace VirtIO block driver using pre-mapped MMIO and DMA pages
- FAT16 filesystem reader serving file-read requests via IPC
- Shared buffer protocol: init writes filename, storage writes file data

Echo app for IPC testing (adapter-loaded echo proved the pipeline end-to-end).
This commit is contained in:
Gabriel Kaszewski
2026-10-18 13:02:30 +02:00
parent ffde4065ba
commit 38f20cc3c4
41 changed files with 1676 additions and 808 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
crates/adapter-riscv/src/hw/mod.rs
View File

@@ -2,3 +2,4 @@ pub mod plic;
pub mod timer;
pub mod uart;
pub mod virtio_blk;
pub mod virtio_gpu;

8
crates/adapter-riscv/src/hw/virtio_blk.rs
View File

@@ -77,11 +77,11 @@ static mut REQ_HEADER: VirtioBlkReqHeader = VirtioBlkReqHeader {
static mut REQ_STATUS: u8 = 0xFF;
fn mmio_read(base: usize, offset: usize) -> u32 {
pub fn mmio_read(base: usize, offset: usize) -> u32 {
unsafe { core::ptr::read_volatile((base + offset) as *const u32) }
}
fn mmio_write(base: usize, offset: usize, val: u32) {
pub fn mmio_write(base: usize, offset: usize, val: u32) {
unsafe { core::ptr::write_volatile((base + offset) as *mut u32, val) }
}
@@ -91,6 +91,10 @@ pub struct VirtioBlk {
}
impl VirtioBlk {
pub fn base(&self) -> usize {
self.base
}
pub fn probe() -> Option<Self> {
for slot in 0..VIRTIO_MMIO_SLOTS {
let base = VIRTIO_MMIO_FIRST + slot * VIRTIO_MMIO_STRIDE;

165
crates/adapter-riscv/src/hw/virtio_gpu.rs Normal file
View File

@@ -0,0 +1,165 @@
const VIRTIO_MAGIC: u32 = 0x74726976;
const VIRTIO_GPU_DEVICE_ID: u32 = 16;
const VIRTIO_MMIO_FIRST: usize = 0x10001000;
const VIRTIO_MMIO_STRIDE: usize = 0x1000;
const VIRTIO_MMIO_SLOTS: usize = 8;
const QUEUE_SIZE: usize = 8;
use super::virtio_blk::{mmio_read, mmio_write};
pub struct VirtioGpu {
base: usize,
}
#[repr(C)]
struct GpuCtrlHdr {
hdr_type: u32,
flags: u32,
fence_id: u64,
ctx_id: u32,
ring_idx: u8,
_pad: [u8; 3],
}
impl VirtioGpu {
pub fn probe() -> Option<Self> {
for slot in 0..VIRTIO_MMIO_SLOTS {
let base = VIRTIO_MMIO_FIRST + slot * VIRTIO_MMIO_STRIDE;
let magic = mmio_read(base, 0x000);
let device_id = mmio_read(base, 0x008);
if magic == VIRTIO_MAGIC && device_id == VIRTIO_GPU_DEVICE_ID {
return Some(Self { base });
}
}
None
}
pub fn base(&self) -> usize {
self.base
}
pub fn init_device(&self, vqueue_phys: usize) {
let base = self.base;
mmio_write(base, 0x070, 0);
while mmio_read(base, 0x070) != 0 {}
mmio_write(base, 0x070, 1); // ACK
mmio_write(base, 0x070, mmio_read(base, 0x070) | 2); // DRIVER
mmio_write(base, 0x028, 4096); // legacy guest page size
mmio_write(base, 0x014, 0); // features sel
mmio_write(base, 0x024, 0); // driver features sel
mmio_write(base, 0x020, 0); // driver features
// controlq (index 0)
mmio_write(base, 0x030, 0);
let qmax = mmio_read(base, 0x034);
let qnum = (QUEUE_SIZE as u32).min(qmax);
mmio_write(base, 0x038, qnum);
mmio_write(base, 0x040, (vqueue_phys / 4096) as u32);
mmio_write(base, 0x070, mmio_read(base, 0x070) | 4); // DRIVER_OK
}
pub fn setup_framebuffer(
&self,
cmd_buf_phys: usize,
vqueue_phys: usize,
fb_phys: usize,
width: u32,
height: u32,
) {
self.send_create_2d(cmd_buf_phys, vqueue_phys, 1, width, height);
self.send_attach_backing(cmd_buf_phys, vqueue_phys, 1, fb_phys, width * height * 4);
self.send_set_scanout(cmd_buf_phys, vqueue_phys, 0, 1, width, height);
}
fn send_cmd(&self, cmd_phys: usize, cmd_len: u32, resp_phys: usize, resp_len: u32, vqueue_phys: usize) {
unsafe {
let descs = vqueue_phys as *mut [u64; 2]; // each desc = addr(u64) + len(u32) + flags(u16) + next(u16)
let desc0 = vqueue_phys as *mut u8;
// desc 0: request (readable)
core::ptr::write_volatile(desc0 as *mut u64, cmd_phys as u64);
core::ptr::write_volatile(desc0.add(8) as *mut u32, cmd_len);
core::ptr::write_volatile(desc0.add(12) as *mut u16, 1); // NEXT
core::ptr::write_volatile(desc0.add(14) as *mut u16, 1); // next=1
// desc 1: response (writable)
let desc1 = desc0.add(16);
core::ptr::write_volatile(desc1 as *mut u64, resp_phys as u64);
core::ptr::write_volatile(desc1.add(8) as *mut u32, resp_len);
core::ptr::write_volatile(desc1.add(12) as *mut u16, 2); // WRITE
core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
// avail ring: after descs (8 descs * 16 bytes = 128 bytes)
let avail = vqueue_phys + QUEUE_SIZE * 16;
let avail_idx = core::ptr::read_volatile((avail + 2) as *const u16);
core::ptr::write_volatile(
(avail + 4 + (avail_idx as usize % QUEUE_SIZE) * 2) as *mut u16,
0,
);
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
core::ptr::write_volatile((avail + 2) as *mut u16, avail_idx.wrapping_add(1));
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
mmio_write(self.base, 0x050, 0); // notify queue 0
// poll used ring (at page boundary = vqueue_phys + 4096)
let used = vqueue_phys + 4096;
let expected = avail_idx.wrapping_add(1);
let mut timeout = 10_000_000u32;
while core::ptr::read_volatile((used + 2) as *const u16) != expected {
core::hint::spin_loop();
timeout -= 1;
if timeout == 0 { return; }
}
}
}
fn send_create_2d(&self, cmd_phys: usize, vq_phys: usize, resource_id: u32, width: u32, height: u32) {
// cmd header (24 bytes) + create_2d fields (16 bytes) = 40 bytes
unsafe {
let p = cmd_phys as *mut u8;
core::ptr::write_bytes(p, 0, 4096);
core::ptr::write_volatile(p as *mut u32, 0x0101); // RESOURCE_CREATE_2D
core::ptr::write_volatile(p.add(24) as *mut u32, resource_id);
core::ptr::write_volatile(p.add(28) as *mut u32, 1); // B8G8R8A8_UNORM
core::ptr::write_volatile(p.add(32) as *mut u32, width);
core::ptr::write_volatile(p.add(36) as *mut u32, height);
}
let resp_phys = cmd_phys + 512;
self.send_cmd(cmd_phys, 40, resp_phys, 24, vq_phys);
}
fn send_attach_backing(&self, cmd_phys: usize, vq_phys: usize, resource_id: u32, fb_phys: usize, fb_size: u32) {
// header (24) + attach_backing (8) + mem_entry (16) = 48 bytes
unsafe {
let p = cmd_phys as *mut u8;
core::ptr::write_bytes(p, 0, 512);
core::ptr::write_volatile(p as *mut u32, 0x0104); // RESOURCE_ATTACH_BACKING
core::ptr::write_volatile(p.add(24) as *mut u32, resource_id);
core::ptr::write_volatile(p.add(28) as *mut u32, 1); // nr_entries
// mem_entry
core::ptr::write_volatile(p.add(32) as *mut u64, fb_phys as u64);
core::ptr::write_volatile(p.add(40) as *mut u32, fb_size);
}
let resp_phys = cmd_phys + 512;
self.send_cmd(cmd_phys, 48, resp_phys, 24, vq_phys);
}
fn send_set_scanout(&self, cmd_phys: usize, vq_phys: usize, scanout_id: u32, resource_id: u32, width: u32, height: u32) {
// header (24) + rect (16) + scanout_id (4) + resource_id (4) = 48 bytes
unsafe {
let p = cmd_phys as *mut u8;
core::ptr::write_bytes(p, 0, 512);
core::ptr::write_volatile(p as *mut u32, 0x0103); // SET_SCANOUT
// rect: x=0, y=0, width, height at offset 24
core::ptr::write_volatile(p.add(32) as *mut u32, width);
core::ptr::write_volatile(p.add(36) as *mut u32, height);
core::ptr::write_volatile(p.add(40) as *mut u32, scanout_id);
core::ptr::write_volatile(p.add(44) as *mut u32, resource_id);
}
let resp_phys = cmd_phys + 512;
self.send_cmd(cmd_phys, 48, resp_phys, 24, vq_phys);
}
}