feat: proper IPC-based boot — init loads servers from storage via IPC, VirtIO GPU driver
Complete microkernel boot pipeline: adapter loads only init + storage + display from disk. Init bootstraps all other servers by reading binaries from the storage server via IPC, parsing ELF, creating processes, mapping pages, and spawning threads. New syscalls: - CreateEndpoint: userspace endpoint creation with full capability grant - DebugPutchar: debug output to UART from userspace - MapPage: cross-process page mapping (init loads binaries into children) - SpawnThreadIn: spawn thread in another process via capability Key fixes: - Per-process L1 page tables for VPN[2]=0 (prevents cross-process corruption) - Separate kernel_pt from page_tables[0] (init pid=0 overwrote kernel PT ref) - Thread Running state set in switch_to_next (syscalls rejected without it) - Pending IPC results applied during context switch - SIE disabled during boot (timer can't preempt into unready processes) - User heap VA starts at 0x40000 (avoids shared buffer at 0x30000) - RequestPages maps at user VAs via per-process heap allocator VirtIO GPU: - Adapter probes for GPU device, initializes resource/scanout/backing - Display server writes to mapped framebuffer, flushes via GPU virtqueue - 640x480 BGRA framebuffer with transfer-to-host and resource-flush Storage server: - Userspace VirtIO block driver using pre-mapped MMIO and DMA pages - FAT16 filesystem reader serving file-read requests via IPC - Shared buffer protocol: init writes filename, storage writes file data Echo app for IPC testing (adapter-loaded echo proved the pipeline end-to-end).
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@@ -1,34 +1,123 @@
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use crate::framebuffer::Framebuffer;
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const VIRTIO_GPU_BASE: usize = 0x10008000;
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const FB_WIDTH: u16 = 640;
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const FB_HEIGHT: u16 = 480;
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const GPU_MMIO_VA: usize = 0x20000;
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const VQUEUE_VA: usize = 0x21000;
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const CMDBUF_VA: usize = 0x23000;
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const PHYSINFO_VA: usize = 0x24000;
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const FB_VA: usize = 0x100000;
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const FB_BPP: usize = 4;
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const QUEUE_SIZE: usize = 8;
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struct PhysInfo {
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cmd_pa: u64,
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resp_pa: u64,
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fb_pa: u64,
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width: u64,
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height: u64,
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}
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fn read_phys_info() -> PhysInfo {
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unsafe {
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let p = PHYSINFO_VA as *const u64;
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PhysInfo {
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cmd_pa: core::ptr::read_volatile(p),
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resp_pa: core::ptr::read_volatile(p.add(1)),
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fb_pa: core::ptr::read_volatile(p.add(2)),
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width: core::ptr::read_volatile(p.add(3)),
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height: core::ptr::read_volatile(p.add(4)),
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}
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}
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}
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fn mmio_write(offset: usize, val: u32) {
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unsafe { core::ptr::write_volatile((GPU_MMIO_VA + offset) as *mut u32, val) }
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}
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pub struct VirtioFramebuffer {
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buffer: &'static mut [u8],
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width: u16,
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height: u16,
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stride: usize,
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phys: PhysInfo,
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}
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impl VirtioFramebuffer {
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pub fn new(buffer_addr: usize) -> Self {
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let stride = FB_WIDTH as usize * FB_BPP;
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let size = stride * FB_HEIGHT as usize;
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let buffer = unsafe { core::slice::from_raw_parts_mut(buffer_addr as *mut u8, size) };
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pub fn new(_buffer_addr: usize) -> Self {
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let phys = read_phys_info();
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let width = phys.width as u16;
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let height = phys.height as u16;
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let stride = width as usize * FB_BPP;
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for byte in buffer.iter_mut() {
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*byte = 0;
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}
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Self { width, height, stride, phys }
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}
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Self {
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buffer,
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width: FB_WIDTH,
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height: FB_HEIGHT,
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stride,
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fn send_gpu_cmd(&self, cmd_len: u32, resp_len: u32) {
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unsafe {
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let desc0 = VQUEUE_VA as *mut u8;
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core::ptr::write_volatile(desc0 as *mut u64, self.phys.cmd_pa);
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core::ptr::write_volatile(desc0.add(8) as *mut u32, cmd_len);
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core::ptr::write_volatile(desc0.add(12) as *mut u16, 1); // NEXT
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core::ptr::write_volatile(desc0.add(14) as *mut u16, 1);
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let desc1 = desc0.add(16);
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core::ptr::write_volatile(desc1 as *mut u64, self.phys.resp_pa);
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core::ptr::write_volatile(desc1.add(8) as *mut u32, resp_len);
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core::ptr::write_volatile(desc1.add(12) as *mut u16, 2); // WRITE
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core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
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let avail = VQUEUE_VA + QUEUE_SIZE * 16;
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let avail_idx = core::ptr::read_volatile((avail + 2) as *const u16);
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core::ptr::write_volatile(
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(avail + 4 + (avail_idx as usize % QUEUE_SIZE) * 2) as *mut u16,
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0,
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);
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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core::ptr::write_volatile((avail + 2) as *mut u16, avail_idx.wrapping_add(1));
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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mmio_write(0x050, 0);
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let used = VQUEUE_VA + 4096;
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let expected = avail_idx.wrapping_add(1);
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let mut timeout = 10_000_000u32;
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while core::ptr::read_volatile((used + 2) as *const u16) != expected {
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core::hint::spin_loop();
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timeout -= 1;
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if timeout == 0 { return; }
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}
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}
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}
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fn transfer_and_flush(&self, x: u32, y: u32, w: u32, h: u32) {
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// TRANSFER_TO_HOST_2D
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unsafe {
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let p = CMDBUF_VA as *mut u8;
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core::ptr::write_bytes(p, 0, 512);
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core::ptr::write_volatile(p as *mut u32, 0x0105); // TRANSFER_TO_HOST_2D
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// rect at offset 24
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core::ptr::write_volatile(p.add(24) as *mut u32, x);
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core::ptr::write_volatile(p.add(28) as *mut u32, y);
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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// offset at 40
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core::ptr::write_volatile(p.add(40) as *mut u64, 0);
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// resource_id at 48
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core::ptr::write_volatile(p.add(48) as *mut u32, 1);
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}
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self.send_gpu_cmd(56, 24);
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// RESOURCE_FLUSH
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unsafe {
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let p = CMDBUF_VA as *mut u8;
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core::ptr::write_bytes(p, 0, 512);
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core::ptr::write_volatile(p as *mut u32, 0x0106); // RESOURCE_FLUSH
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core::ptr::write_volatile(p.add(24) as *mut u32, x);
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core::ptr::write_volatile(p.add(28) as *mut u32, y);
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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core::ptr::write_volatile(p.add(40) as *mut u32, 1); // resource_id
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}
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self.send_gpu_cmd(48, 24);
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}
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}
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impl Framebuffer for VirtioFramebuffer {
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@@ -41,15 +130,12 @@ impl Framebuffer for VirtioFramebuffer {
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}
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fn write_pixel(&mut self, x: u16, y: u16, color: u32) {
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if x >= self.width || y >= self.height {
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return;
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}
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if x >= self.width || y >= self.height { return; }
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let offset = (y as usize) * self.stride + (x as usize) * FB_BPP;
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let bytes = color.to_le_bytes();
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self.buffer[offset] = bytes[0];
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self.buffer[offset + 1] = bytes[1];
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self.buffer[offset + 2] = bytes[2];
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self.buffer[offset + 3] = bytes[3];
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let buf = FB_VA + offset;
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unsafe {
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core::ptr::write_volatile(buf as *mut u32, color);
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}
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}
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fn fill_rect(&mut self, x: u16, y: u16, w: u16, h: u16, color: u32) {
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@@ -61,21 +147,14 @@ impl Framebuffer for VirtioFramebuffer {
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}
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fn clear(&mut self, color: u32) {
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let bytes = color.to_le_bytes();
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for y in 0..self.height as usize {
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for x in 0..self.width as usize {
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let offset = y * self.stride + x * FB_BPP;
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self.buffer[offset] = bytes[0];
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self.buffer[offset + 1] = bytes[1];
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self.buffer[offset + 2] = bytes[2];
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self.buffer[offset + 3] = bytes[3];
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}
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let total = self.width as usize * self.height as usize;
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let buf = FB_VA as *mut u32;
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for i in 0..total {
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unsafe { core::ptr::write_volatile(buf.add(i), color); }
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}
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}
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fn flush(&mut self) {
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// VirtIO GPU flush would send TRANSFER_TO_HOST_2D + RESOURCE_FLUSH
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// For now, the buffer is memory-mapped — no explicit flush needed
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// when using ramfb or a simple scanout
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self.transfer_and_flush(0, 0, self.width as u32, self.height as u32);
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}
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}
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