refactor: extract shared hw-virtio crate, eliminate VirtIO protocol duplication
Two VirtIO block and two VirtIO GPU implementations (adapter + driver)
shared 90% of their protocol logic. Extracted the common code into
hw-virtio, parameterized by MmioAccess trait.
New crate: hw-virtio (no_std, zero deps)
- mmio.rs: MmioAccess trait, DirectMmio, init_legacy_device(), scan
- queue.rs: VirtioQueue with descriptor chain submit + poll
- block.rs: block read protocol (3-descriptor chain)
- gpu.rs: GPU commands (create_2d, attach_backing, set_scanout,
transfer_to_host, resource_flush)
Adapter thin wrappers (identity-mapped, statics for DMA):
- virtio_blk.rs: 220 → 53 lines
- virtio_gpu.rs: 165 → 37 lines
Driver thin wrappers (mapped VAs, phys-info for DMA):
- drivers/block/virtio: 139 → 70 lines
- drivers/framebuffer/virtio: 146 → 95 lines
Also deleted input-server/input_device.rs (1-line re-export,
superseded by port-input-device).
This commit is contained in:
@@ -1,5 +1,4 @@
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use crate::hw::uart::Uart;
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use crate::hw::virtio_blk::{mmio_read, mmio_write};
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use crate::{kernel_ref, mmu};
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use types::id::ProcessId;
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@@ -86,22 +85,8 @@ fn write_phys_info(pt: &mut mmu::PageTable, reqhdr_phys: usize) {
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}
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fn reinit_device(base: usize, vqueue_phys: usize) {
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mmio_write(base, 0x070, 0);
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while mmio_read(base, 0x070) != 0 {}
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mmio_write(base, 0x070, 1);
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mmio_write(base, 0x070, mmio_read(base, 0x070) | 2);
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mmio_write(base, 0x028, 4096);
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mmio_write(base, 0x014, 0);
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mmio_write(base, 0x024, 0);
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mmio_write(base, 0x020, 0);
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mmio_write(base, 0x030, 0);
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let queue_max = mmio_read(base, 0x034);
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mmio_write(base, 0x038, 8u32.min(queue_max));
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mmio_write(base, 0x040, (vqueue_phys / 4096) as u32);
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mmio_write(base, 0x070, mmio_read(base, 0x070) | 4);
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let mmio = hw_virtio::mmio::DirectMmio::new(base);
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hw_virtio::mmio::init_legacy_device(&mmio, vqueue_phys, hw_virtio::queue::QUEUE_SIZE as u32);
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}
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fn map_shared_buffer(init_pt: &mut mmu::PageTable, storage_pt: &mut mmu::PageTable) {
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@@ -1,220 +1,53 @@
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const VIRTIO_MAGIC: u32 = 0x74726976;
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const VIRTIO_BLK_DEVICE_ID: u32 = 2;
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const VIRTIO_MMIO_FIRST: usize = 0x10001000;
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const VIRTIO_MMIO_STRIDE: usize = 0x1000;
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const VIRTIO_MMIO_SLOTS: usize = 8;
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use hw_virtio::mmio::{self, DirectMmio};
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use hw_virtio::queue::{QueueAddrs, VirtioQueue, QUEUE_SIZE};
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use hw_virtio::block::{self, DmaAddrs};
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const VIRTIO_STATUS_ACK: u32 = 1;
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const VIRTIO_STATUS_DRIVER: u32 = 2;
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const VIRTIO_STATUS_FEATURES_OK: u32 = 8;
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const VIRTIO_STATUS_DRIVER_OK: u32 = 4;
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const QUEUE_SIZE: usize = 8;
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const SECTOR_SIZE: usize = 512;
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const PAGE_SIZE: usize = 4096;
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// Legacy VirtIO layout: used ring must start at page boundary after avail ring.
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// descs: 8 * 16 = 128 bytes, avail: 22 bytes → total 150 → pad to 4096.
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#[repr(C, align(4096))]
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struct VirtqMem {
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descs: [VirtqDesc; QUEUE_SIZE],
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avail: VirtqAvail,
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_pad: [u8; 3946],
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used: VirtqUsed,
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_data: [u8; 8192],
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}
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#[repr(C)]
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#[derive(Clone, Copy)]
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struct VirtqDesc {
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addr: u64,
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len: u32,
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flags: u16,
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next: u16,
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}
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#[repr(C)]
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struct VirtqAvail {
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flags: u16,
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idx: u16,
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ring: [u16; QUEUE_SIZE],
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used_event: u16,
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}
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#[repr(C)]
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struct VirtqUsed {
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flags: u16,
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idx: u16,
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ring: [VirtqUsedElem; QUEUE_SIZE],
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}
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#[repr(C)]
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#[derive(Clone, Copy)]
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struct VirtqUsedElem {
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id: u32,
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len: u32,
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}
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#[repr(C)]
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struct VirtioBlkReqHeader {
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req_type: u32,
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reserved: u32,
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sector: u64,
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}
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static mut VQUEUE: VirtqMem = VirtqMem {
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descs: [const { VirtqDesc { addr: 0, len: 0, flags: 0, next: 0 } }; QUEUE_SIZE],
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avail: VirtqAvail { flags: 0, idx: 0, ring: [0; QUEUE_SIZE], used_event: 0 },
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_pad: [0; 3946],
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used: VirtqUsed {
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flags: 0, idx: 0,
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ring: [const { VirtqUsedElem { id: 0, len: 0 } }; QUEUE_SIZE],
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},
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};
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static mut REQ_HEADER: VirtioBlkReqHeader = VirtioBlkReqHeader {
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req_type: 0, reserved: 0, sector: 0,
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};
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static mut VQUEUE: VirtqMem = VirtqMem { _data: [0; 8192] };
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static mut REQ_HEADER: block::BlockReqHeader = block::BlockReqHeader { req_type: 0, reserved: 0, sector: 0 };
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static mut REQ_STATUS: u8 = 0xFF;
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pub fn mmio_read(base: usize, offset: usize) -> u32 {
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unsafe { core::ptr::read_volatile((base + offset) as *const u32) }
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}
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pub fn mmio_write(base: usize, offset: usize, val: u32) {
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unsafe { core::ptr::write_volatile((base + offset) as *mut u32, val) }
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}
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static mut SECTOR_BUF: [u8; SECTOR_SIZE] = [0; SECTOR_SIZE];
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pub struct VirtioBlk {
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base: usize,
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legacy: bool,
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mmio: DirectMmio,
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queue: VirtioQueue,
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dma: DmaAddrs,
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}
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impl VirtioBlk {
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pub fn base(&self) -> usize {
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self.base
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}
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pub fn probe() -> Option<Self> {
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for slot in 0..VIRTIO_MMIO_SLOTS {
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let base = VIRTIO_MMIO_FIRST + slot * VIRTIO_MMIO_STRIDE;
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let magic = mmio_read(base, 0x000);
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let device_id = mmio_read(base, 0x008);
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if magic == VIRTIO_MAGIC && device_id == VIRTIO_BLK_DEVICE_ID {
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return Self::init_at(base);
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let mmio = mmio::scan_for_device(mmio::DEVICE_ID_BLOCK)?;
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let vq_phys = unsafe { core::ptr::addr_of!(VQUEUE) as usize };
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mmio::init_legacy_device(&mmio, vq_phys, QUEUE_SIZE as u32);
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let queue = VirtioQueue::new(QueueAddrs::from_base(vq_phys));
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let dma = unsafe {
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DmaAddrs {
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header_pa: core::ptr::addr_of!(REQ_HEADER) as u64,
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header_va: core::ptr::addr_of_mut!(REQ_HEADER) as usize,
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status_pa: core::ptr::addr_of!(REQ_STATUS) as u64,
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status_va: core::ptr::addr_of_mut!(REQ_STATUS) as usize,
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data_pa: core::ptr::addr_of!(SECTOR_BUF) as u64,
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data_va: core::ptr::addr_of_mut!(SECTOR_BUF) as usize,
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}
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}
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None
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};
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Some(Self { mmio, queue, dma })
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}
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fn init_at(base: usize) -> Option<Self> {
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let version = mmio_read(base, 0x004);
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let legacy = version == 1;
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// Reset
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mmio_write(base, 0x070, 0);
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while mmio_read(base, 0x070) != 0 {}
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// Acknowledge + Driver
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mmio_write(base, 0x070, VIRTIO_STATUS_ACK);
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mmio_write(base, 0x070, mmio_read(base, 0x070) | VIRTIO_STATUS_DRIVER);
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if legacy {
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// Legacy: set guest page size
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mmio_write(base, 0x028, PAGE_SIZE as u32);
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}
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// Feature negotiation
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mmio_write(base, 0x014, 0);
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let _features = mmio_read(base, 0x010);
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mmio_write(base, 0x024, 0);
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mmio_write(base, 0x020, 0);
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if !legacy {
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mmio_write(base, 0x070, mmio_read(base, 0x070) | VIRTIO_STATUS_FEATURES_OK);
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if mmio_read(base, 0x070) & VIRTIO_STATUS_FEATURES_OK == 0 {
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return None;
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}
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}
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// Queue setup
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mmio_write(base, 0x030, 0);
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let queue_max = mmio_read(base, 0x034);
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if queue_max == 0 { return None; }
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let queue_num = (QUEUE_SIZE as u32).min(queue_max);
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mmio_write(base, 0x038, queue_num);
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unsafe {
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let vq_addr = core::ptr::addr_of!(VQUEUE) as usize;
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if legacy {
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mmio_write(base, 0x040, (vq_addr / PAGE_SIZE) as u32);
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} else {
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let desc_addr = vq_addr as u64;
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let avail_addr = (vq_addr + core::mem::offset_of!(VirtqMem, avail)) as u64;
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let used_addr = (vq_addr + core::mem::offset_of!(VirtqMem, used)) as u64;
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mmio_write(base, 0x080, desc_addr as u32);
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mmio_write(base, 0x084, (desc_addr >> 32) as u32);
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mmio_write(base, 0x090, avail_addr as u32);
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mmio_write(base, 0x094, (avail_addr >> 32) as u32);
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mmio_write(base, 0x0A0, used_addr as u32);
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mmio_write(base, 0x0A4, (used_addr >> 32) as u32);
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mmio_write(base, 0x044, 1);
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}
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}
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mmio_write(base, 0x070, mmio_read(base, 0x070) | VIRTIO_STATUS_DRIVER_OK);
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Some(Self { base, legacy })
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pub fn base(&self) -> usize {
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self.mmio.base()
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}
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pub fn read_sector(&mut self, sector: u32, buf: &mut [u8; SECTOR_SIZE]) -> bool {
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unsafe {
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REQ_HEADER.req_type = 0;
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REQ_HEADER.reserved = 0;
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REQ_HEADER.sector = sector as u64;
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REQ_STATUS = 0xFF;
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VQUEUE.descs[0] = VirtqDesc {
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addr: core::ptr::addr_of!(REQ_HEADER) as u64,
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len: 16,
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flags: 1, // NEXT
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next: 1,
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};
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VQUEUE.descs[1] = VirtqDesc {
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addr: buf.as_ptr() as u64,
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len: SECTOR_SIZE as u32,
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flags: 2 | 1, // WRITE | NEXT
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next: 2,
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};
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VQUEUE.descs[2] = VirtqDesc {
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addr: core::ptr::addr_of!(REQ_STATUS) as u64,
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len: 1,
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flags: 2, // WRITE
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next: 0,
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};
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let avail_idx = core::ptr::read_volatile(core::ptr::addr_of!(VQUEUE.avail.idx));
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VQUEUE.avail.ring[(avail_idx as usize) % QUEUE_SIZE] = 0;
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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core::ptr::write_volatile(
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core::ptr::addr_of_mut!(VQUEUE.avail.idx),
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avail_idx.wrapping_add(1),
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);
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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mmio_write(self.base, 0x050, 0);
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let expected = avail_idx.wrapping_add(1);
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let mut timeout = 10_000_000u32;
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while core::ptr::read_volatile(core::ptr::addr_of!(VQUEUE.used.idx)) != expected {
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core::hint::spin_loop();
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timeout -= 1;
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if timeout == 0 { return false; }
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}
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REQ_STATUS == 0
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}
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block::read_sector(&self.mmio, &self.queue, &self.dma, sector, buf)
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}
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}
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@@ -1,165 +1,34 @@
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const VIRTIO_MAGIC: u32 = 0x74726976;
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const VIRTIO_GPU_DEVICE_ID: u32 = 16;
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const VIRTIO_MMIO_FIRST: usize = 0x10001000;
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const VIRTIO_MMIO_STRIDE: usize = 0x1000;
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const VIRTIO_MMIO_SLOTS: usize = 8;
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const QUEUE_SIZE: usize = 8;
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use super::virtio_blk::{mmio_read, mmio_write};
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use hw_virtio::mmio::{self, DirectMmio};
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use hw_virtio::queue::{QueueAddrs, VirtioQueue, QUEUE_SIZE};
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use hw_virtio::gpu::{self, GpuDmaAddrs};
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pub struct VirtioGpu {
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base: usize,
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}
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#[repr(C)]
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struct GpuCtrlHdr {
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hdr_type: u32,
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flags: u32,
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fence_id: u64,
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ctx_id: u32,
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ring_idx: u8,
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_pad: [u8; 3],
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mmio: DirectMmio,
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}
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impl VirtioGpu {
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pub fn probe() -> Option<Self> {
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for slot in 0..VIRTIO_MMIO_SLOTS {
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let base = VIRTIO_MMIO_FIRST + slot * VIRTIO_MMIO_STRIDE;
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let magic = mmio_read(base, 0x000);
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let device_id = mmio_read(base, 0x008);
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if magic == VIRTIO_MAGIC && device_id == VIRTIO_GPU_DEVICE_ID {
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return Some(Self { base });
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}
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}
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None
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let mmio = mmio::scan_for_device(mmio::DEVICE_ID_GPU)?;
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Some(Self { mmio })
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}
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pub fn base(&self) -> usize {
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self.base
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self.mmio.base()
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}
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pub fn init_device(&self, vqueue_phys: usize) {
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let base = self.base;
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mmio_write(base, 0x070, 0);
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while mmio_read(base, 0x070) != 0 {}
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mmio_write(base, 0x070, 1); // ACK
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mmio_write(base, 0x070, mmio_read(base, 0x070) | 2); // DRIVER
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mmio_write(base, 0x028, 4096); // legacy guest page size
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mmio_write(base, 0x014, 0); // features sel
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mmio_write(base, 0x024, 0); // driver features sel
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mmio_write(base, 0x020, 0); // driver features
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// controlq (index 0)
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mmio_write(base, 0x030, 0);
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let qmax = mmio_read(base, 0x034);
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let qnum = (QUEUE_SIZE as u32).min(qmax);
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mmio_write(base, 0x038, qnum);
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mmio_write(base, 0x040, (vqueue_phys / 4096) as u32);
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mmio_write(base, 0x070, mmio_read(base, 0x070) | 4); // DRIVER_OK
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mmio::init_legacy_device(&self.mmio, vqueue_phys, QUEUE_SIZE as u32);
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}
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pub fn setup_framebuffer(
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&self,
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cmd_buf_phys: usize,
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vqueue_phys: usize,
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fb_phys: usize,
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width: u32,
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height: u32,
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) {
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self.send_create_2d(cmd_buf_phys, vqueue_phys, 1, width, height);
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self.send_attach_backing(cmd_buf_phys, vqueue_phys, 1, fb_phys, width * height * 4);
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self.send_set_scanout(cmd_buf_phys, vqueue_phys, 0, 1, width, height);
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}
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fn send_cmd(&self, cmd_phys: usize, cmd_len: u32, resp_phys: usize, resp_len: u32, vqueue_phys: usize) {
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unsafe {
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let descs = vqueue_phys as *mut [u64; 2]; // each desc = addr(u64) + len(u32) + flags(u16) + next(u16)
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let desc0 = vqueue_phys as *mut u8;
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// desc 0: request (readable)
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core::ptr::write_volatile(desc0 as *mut u64, cmd_phys as u64);
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core::ptr::write_volatile(desc0.add(8) as *mut u32, cmd_len);
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core::ptr::write_volatile(desc0.add(12) as *mut u16, 1); // NEXT
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core::ptr::write_volatile(desc0.add(14) as *mut u16, 1); // next=1
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// desc 1: response (writable)
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let desc1 = desc0.add(16);
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core::ptr::write_volatile(desc1 as *mut u64, resp_phys as u64);
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core::ptr::write_volatile(desc1.add(8) as *mut u32, resp_len);
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core::ptr::write_volatile(desc1.add(12) as *mut u16, 2); // WRITE
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core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
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// avail ring: after descs (8 descs * 16 bytes = 128 bytes)
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let avail = vqueue_phys + QUEUE_SIZE * 16;
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let avail_idx = core::ptr::read_volatile((avail + 2) as *const u16);
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core::ptr::write_volatile(
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(avail + 4 + (avail_idx as usize % QUEUE_SIZE) * 2) as *mut u16,
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0,
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);
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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core::ptr::write_volatile((avail + 2) as *mut u16, avail_idx.wrapping_add(1));
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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mmio_write(self.base, 0x050, 0); // notify queue 0
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// poll used ring (at page boundary = vqueue_phys + 4096)
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let used = vqueue_phys + 4096;
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let expected = avail_idx.wrapping_add(1);
|
||||
let mut timeout = 10_000_000u32;
|
||||
while core::ptr::read_volatile((used + 2) as *const u16) != expected {
|
||||
core::hint::spin_loop();
|
||||
timeout -= 1;
|
||||
if timeout == 0 { return; }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn send_create_2d(&self, cmd_phys: usize, vq_phys: usize, resource_id: u32, width: u32, height: u32) {
|
||||
// cmd header (24 bytes) + create_2d fields (16 bytes) = 40 bytes
|
||||
unsafe {
|
||||
let p = cmd_phys as *mut u8;
|
||||
core::ptr::write_bytes(p, 0, 4096);
|
||||
core::ptr::write_volatile(p as *mut u32, 0x0101); // RESOURCE_CREATE_2D
|
||||
core::ptr::write_volatile(p.add(24) as *mut u32, resource_id);
|
||||
core::ptr::write_volatile(p.add(28) as *mut u32, 1); // B8G8R8A8_UNORM
|
||||
core::ptr::write_volatile(p.add(32) as *mut u32, width);
|
||||
core::ptr::write_volatile(p.add(36) as *mut u32, height);
|
||||
}
|
||||
let resp_phys = cmd_phys + 512;
|
||||
self.send_cmd(cmd_phys, 40, resp_phys, 24, vq_phys);
|
||||
}
|
||||
|
||||
fn send_attach_backing(&self, cmd_phys: usize, vq_phys: usize, resource_id: u32, fb_phys: usize, fb_size: u32) {
|
||||
// header (24) + attach_backing (8) + mem_entry (16) = 48 bytes
|
||||
unsafe {
|
||||
let p = cmd_phys as *mut u8;
|
||||
core::ptr::write_bytes(p, 0, 512);
|
||||
core::ptr::write_volatile(p as *mut u32, 0x0104); // RESOURCE_ATTACH_BACKING
|
||||
core::ptr::write_volatile(p.add(24) as *mut u32, resource_id);
|
||||
core::ptr::write_volatile(p.add(28) as *mut u32, 1); // nr_entries
|
||||
// mem_entry
|
||||
core::ptr::write_volatile(p.add(32) as *mut u64, fb_phys as u64);
|
||||
core::ptr::write_volatile(p.add(40) as *mut u32, fb_size);
|
||||
}
|
||||
let resp_phys = cmd_phys + 512;
|
||||
self.send_cmd(cmd_phys, 48, resp_phys, 24, vq_phys);
|
||||
}
|
||||
|
||||
fn send_set_scanout(&self, cmd_phys: usize, vq_phys: usize, scanout_id: u32, resource_id: u32, width: u32, height: u32) {
|
||||
// header (24) + rect (16) + scanout_id (4) + resource_id (4) = 48 bytes
|
||||
unsafe {
|
||||
let p = cmd_phys as *mut u8;
|
||||
core::ptr::write_bytes(p, 0, 512);
|
||||
core::ptr::write_volatile(p as *mut u32, 0x0103); // SET_SCANOUT
|
||||
// rect: x=0, y=0, width, height at offset 24
|
||||
core::ptr::write_volatile(p.add(32) as *mut u32, width);
|
||||
core::ptr::write_volatile(p.add(36) as *mut u32, height);
|
||||
core::ptr::write_volatile(p.add(40) as *mut u32, scanout_id);
|
||||
core::ptr::write_volatile(p.add(44) as *mut u32, resource_id);
|
||||
}
|
||||
let resp_phys = cmd_phys + 512;
|
||||
self.send_cmd(cmd_phys, 48, resp_phys, 24, vq_phys);
|
||||
pub fn setup_framebuffer(&self, cmd_phys: usize, vq_phys: usize, fb_phys: usize, width: u32, height: u32) {
|
||||
let queue = VirtioQueue::new(QueueAddrs::from_base(vq_phys));
|
||||
let dma = GpuDmaAddrs {
|
||||
cmd_pa: cmd_phys as u64,
|
||||
cmd_va: cmd_phys,
|
||||
resp_pa: (cmd_phys + 512) as u64,
|
||||
};
|
||||
gpu::create_2d(&self.mmio, &queue, &dma, 1, width, height);
|
||||
gpu::attach_backing(&self.mmio, &queue, &dma, 1, fb_phys as u64, width * height * 4);
|
||||
gpu::set_scanout(&self.mmio, &queue, &dma, 0, 1, width, height);
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user