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refactor: extract shared hw-virtio crate, eliminate VirtIO protocol duplication

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Two VirtIO block and two VirtIO GPU implementations (adapter + driver)
shared 90% of their protocol logic. Extracted the common code into
hw-virtio, parameterized by MmioAccess trait.

New crate: hw-virtio (no_std, zero deps)
  - mmio.rs: MmioAccess trait, DirectMmio, init_legacy_device(), scan
  - queue.rs: VirtioQueue with descriptor chain submit + poll
  - block.rs: block read protocol (3-descriptor chain)
  - gpu.rs: GPU commands (create_2d, attach_backing, set_scanout,
            transfer_to_host, resource_flush)

Adapter thin wrappers (identity-mapped, statics for DMA):
  - virtio_blk.rs: 220 → 53 lines
  - virtio_gpu.rs: 165 → 37 lines

Driver thin wrappers (mapped VAs, phys-info for DMA):
  - drivers/block/virtio: 139 → 70 lines
  - drivers/framebuffer/virtio: 146 → 95 lines

Also deleted input-server/input_device.rs (1-line re-export,
superseded by port-input-device).
This commit is contained in:
Gabriel Kaszewski
2026-10-18 13:29:28 +02:00
parent 8d53fa9ac5
commit 3a0395453b
21 changed files with 483 additions and 562 deletions
Download Patch File Download Diff File Expand all files Collapse all files

229
crates/adapter-riscv/src/hw/virtio_blk.rs
View File

@@ -1,220 +1,53 @@
const VIRTIO_MAGIC: u32 = 0x74726976;
const VIRTIO_BLK_DEVICE_ID: u32 = 2;
const VIRTIO_MMIO_FIRST: usize = 0x10001000;
const VIRTIO_MMIO_STRIDE: usize = 0x1000;
const VIRTIO_MMIO_SLOTS: usize = 8;
use hw_virtio::mmio::{self, DirectMmio};
use hw_virtio::queue::{QueueAddrs, VirtioQueue, QUEUE_SIZE};
use hw_virtio::block::{self, DmaAddrs};
const VIRTIO_STATUS_ACK: u32 = 1;
const VIRTIO_STATUS_DRIVER: u32 = 2;
const VIRTIO_STATUS_FEATURES_OK: u32 = 8;
const VIRTIO_STATUS_DRIVER_OK: u32 = 4;
const QUEUE_SIZE: usize = 8;
const SECTOR_SIZE: usize = 512;
const PAGE_SIZE: usize = 4096;
// Legacy VirtIO layout: used ring must start at page boundary after avail ring.
// descs: 8 * 16 = 128 bytes, avail: 22 bytes → total 150 → pad to 4096.
#[repr(C, align(4096))]
struct VirtqMem {
descs: [VirtqDesc; QUEUE_SIZE],
avail: VirtqAvail,
_pad: [u8; 3946],
used: VirtqUsed,
_data: [u8; 8192],
}
#[repr(C)]
#[derive(Clone, Copy)]
struct VirtqDesc {
addr: u64,
len: u32,
flags: u16,
next: u16,
}
#[repr(C)]
struct VirtqAvail {
flags: u16,
idx: u16,
ring: [u16; QUEUE_SIZE],
used_event: u16,
}
#[repr(C)]
struct VirtqUsed {
flags: u16,
idx: u16,
ring: [VirtqUsedElem; QUEUE_SIZE],
}
#[repr(C)]
#[derive(Clone, Copy)]
struct VirtqUsedElem {
id: u32,
len: u32,
}
#[repr(C)]
struct VirtioBlkReqHeader {
req_type: u32,
reserved: u32,
sector: u64,
}
static mut VQUEUE: VirtqMem = VirtqMem {
descs: [const { VirtqDesc { addr: 0, len: 0, flags: 0, next: 0 } }; QUEUE_SIZE],
avail: VirtqAvail { flags: 0, idx: 0, ring: [0; QUEUE_SIZE], used_event: 0 },
_pad: [0; 3946],
used: VirtqUsed {
flags: 0, idx: 0,
ring: [const { VirtqUsedElem { id: 0, len: 0 } }; QUEUE_SIZE],
},
};
static mut REQ_HEADER: VirtioBlkReqHeader = VirtioBlkReqHeader {
req_type: 0, reserved: 0, sector: 0,
};
static mut VQUEUE: VirtqMem = VirtqMem { _data: [0; 8192] };
static mut REQ_HEADER: block::BlockReqHeader = block::BlockReqHeader { req_type: 0, reserved: 0, sector: 0 };
static mut REQ_STATUS: u8 = 0xFF;
pub fn mmio_read(base: usize, offset: usize) -> u32 {
unsafe { core::ptr::read_volatile((base + offset) as *const u32) }
}
pub fn mmio_write(base: usize, offset: usize, val: u32) {
unsafe { core::ptr::write_volatile((base + offset) as *mut u32, val) }
}
static mut SECTOR_BUF: [u8; SECTOR_SIZE] = [0; SECTOR_SIZE];
pub struct VirtioBlk {
base: usize,
legacy: bool,
mmio: DirectMmio,
queue: VirtioQueue,
dma: DmaAddrs,
}
impl VirtioBlk {
pub fn base(&self) -> usize {
self.base
}
pub fn probe() -> Option<Self> {
for slot in 0..VIRTIO_MMIO_SLOTS {
let base = VIRTIO_MMIO_FIRST + slot * VIRTIO_MMIO_STRIDE;
let magic = mmio_read(base, 0x000);
let device_id = mmio_read(base, 0x008);
if magic == VIRTIO_MAGIC && device_id == VIRTIO_BLK_DEVICE_ID {
return Self::init_at(base);
let mmio = mmio::scan_for_device(mmio::DEVICE_ID_BLOCK)?;
let vq_phys = unsafe { core::ptr::addr_of!(VQUEUE) as usize };
mmio::init_legacy_device(&mmio, vq_phys, QUEUE_SIZE as u32);
let queue = VirtioQueue::new(QueueAddrs::from_base(vq_phys));
let dma = unsafe {
DmaAddrs {
header_pa: core::ptr::addr_of!(REQ_HEADER) as u64,
header_va: core::ptr::addr_of_mut!(REQ_HEADER) as usize,
status_pa: core::ptr::addr_of!(REQ_STATUS) as u64,
status_va: core::ptr::addr_of_mut!(REQ_STATUS) as usize,
data_pa: core::ptr::addr_of!(SECTOR_BUF) as u64,
data_va: core::ptr::addr_of_mut!(SECTOR_BUF) as usize,
}
}
None
};
Some(Self { mmio, queue, dma })
}
fn init_at(base: usize) -> Option<Self> {
let version = mmio_read(base, 0x004);
let legacy = version == 1;
// Reset
mmio_write(base, 0x070, 0);
while mmio_read(base, 0x070) != 0 {}
// Acknowledge + Driver
mmio_write(base, 0x070, VIRTIO_STATUS_ACK);
mmio_write(base, 0x070, mmio_read(base, 0x070) | VIRTIO_STATUS_DRIVER);
if legacy {
// Legacy: set guest page size
mmio_write(base, 0x028, PAGE_SIZE as u32);
}
// Feature negotiation
mmio_write(base, 0x014, 0);
let _features = mmio_read(base, 0x010);
mmio_write(base, 0x024, 0);
mmio_write(base, 0x020, 0);
if !legacy {
mmio_write(base, 0x070, mmio_read(base, 0x070) | VIRTIO_STATUS_FEATURES_OK);
if mmio_read(base, 0x070) & VIRTIO_STATUS_FEATURES_OK == 0 {
return None;
}
}
// Queue setup
mmio_write(base, 0x030, 0);
let queue_max = mmio_read(base, 0x034);
if queue_max == 0 { return None; }
let queue_num = (QUEUE_SIZE as u32).min(queue_max);
mmio_write(base, 0x038, queue_num);
unsafe {
let vq_addr = core::ptr::addr_of!(VQUEUE) as usize;
if legacy {
mmio_write(base, 0x040, (vq_addr / PAGE_SIZE) as u32);
} else {
let desc_addr = vq_addr as u64;
let avail_addr = (vq_addr + core::mem::offset_of!(VirtqMem, avail)) as u64;
let used_addr = (vq_addr + core::mem::offset_of!(VirtqMem, used)) as u64;
mmio_write(base, 0x080, desc_addr as u32);
mmio_write(base, 0x084, (desc_addr >> 32) as u32);
mmio_write(base, 0x090, avail_addr as u32);
mmio_write(base, 0x094, (avail_addr >> 32) as u32);
mmio_write(base, 0x0A0, used_addr as u32);
mmio_write(base, 0x0A4, (used_addr >> 32) as u32);
mmio_write(base, 0x044, 1);
}
}
mmio_write(base, 0x070, mmio_read(base, 0x070) | VIRTIO_STATUS_DRIVER_OK);
Some(Self { base, legacy })
pub fn base(&self) -> usize {
self.mmio.base()
}
pub fn read_sector(&mut self, sector: u32, buf: &mut [u8; SECTOR_SIZE]) -> bool {
unsafe {
REQ_HEADER.req_type = 0;
REQ_HEADER.reserved = 0;
REQ_HEADER.sector = sector as u64;
REQ_STATUS = 0xFF;
VQUEUE.descs[0] = VirtqDesc {
addr: core::ptr::addr_of!(REQ_HEADER) as u64,
len: 16,
flags: 1, // NEXT
next: 1,
};
VQUEUE.descs[1] = VirtqDesc {
addr: buf.as_ptr() as u64,
len: SECTOR_SIZE as u32,
flags: 2 | 1, // WRITE | NEXT
next: 2,
};
VQUEUE.descs[2] = VirtqDesc {
addr: core::ptr::addr_of!(REQ_STATUS) as u64,
len: 1,
flags: 2, // WRITE
next: 0,
};
let avail_idx = core::ptr::read_volatile(core::ptr::addr_of!(VQUEUE.avail.idx));
VQUEUE.avail.ring[(avail_idx as usize) % QUEUE_SIZE] = 0;
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
core::ptr::write_volatile(
core::ptr::addr_of_mut!(VQUEUE.avail.idx),
avail_idx.wrapping_add(1),
);
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
mmio_write(self.base, 0x050, 0);
let expected = avail_idx.wrapping_add(1);
let mut timeout = 10_000_000u32;
while core::ptr::read_volatile(core::ptr::addr_of!(VQUEUE.used.idx)) != expected {
core::hint::spin_loop();
timeout -= 1;
if timeout == 0 { return false; }
}
REQ_STATUS == 0
}
block::read_sector(&self.mmio, &self.queue, &self.dma, sector, buf)
}
}

167
crates/adapter-riscv/src/hw/virtio_gpu.rs
View File

@@ -1,165 +1,34 @@
const VIRTIO_MAGIC: u32 = 0x74726976;
const VIRTIO_GPU_DEVICE_ID: u32 = 16;
const VIRTIO_MMIO_FIRST: usize = 0x10001000;
const VIRTIO_MMIO_STRIDE: usize = 0x1000;
const VIRTIO_MMIO_SLOTS: usize = 8;
const QUEUE_SIZE: usize = 8;
use super::virtio_blk::{mmio_read, mmio_write};
use hw_virtio::mmio::{self, DirectMmio};
use hw_virtio::queue::{QueueAddrs, VirtioQueue, QUEUE_SIZE};
use hw_virtio::gpu::{self, GpuDmaAddrs};
pub struct VirtioGpu {
base: usize,
}
#[repr(C)]
struct GpuCtrlHdr {
hdr_type: u32,
flags: u32,
fence_id: u64,
ctx_id: u32,
ring_idx: u8,
_pad: [u8; 3],
mmio: DirectMmio,
}
impl VirtioGpu {
pub fn probe() -> Option<Self> {
for slot in 0..VIRTIO_MMIO_SLOTS {
let base = VIRTIO_MMIO_FIRST + slot * VIRTIO_MMIO_STRIDE;
let magic = mmio_read(base, 0x000);
let device_id = mmio_read(base, 0x008);
if magic == VIRTIO_MAGIC && device_id == VIRTIO_GPU_DEVICE_ID {
return Some(Self { base });
}
}
None
let mmio = mmio::scan_for_device(mmio::DEVICE_ID_GPU)?;
Some(Self { mmio })
}
pub fn base(&self) -> usize {
self.base
self.mmio.base()
}
pub fn init_device(&self, vqueue_phys: usize) {
let base = self.base;
mmio_write(base, 0x070, 0);
while mmio_read(base, 0x070) != 0 {}
mmio_write(base, 0x070, 1); // ACK
mmio_write(base, 0x070, mmio_read(base, 0x070) | 2); // DRIVER
mmio_write(base, 0x028, 4096); // legacy guest page size
mmio_write(base, 0x014, 0); // features sel
mmio_write(base, 0x024, 0); // driver features sel
mmio_write(base, 0x020, 0); // driver features
// controlq (index 0)
mmio_write(base, 0x030, 0);
let qmax = mmio_read(base, 0x034);
let qnum = (QUEUE_SIZE as u32).min(qmax);
mmio_write(base, 0x038, qnum);
mmio_write(base, 0x040, (vqueue_phys / 4096) as u32);
mmio_write(base, 0x070, mmio_read(base, 0x070) | 4); // DRIVER_OK
mmio::init_legacy_device(&self.mmio, vqueue_phys, QUEUE_SIZE as u32);
}
pub fn setup_framebuffer(
&self,
cmd_buf_phys: usize,
vqueue_phys: usize,
fb_phys: usize,
width: u32,
height: u32,
) {
self.send_create_2d(cmd_buf_phys, vqueue_phys, 1, width, height);
self.send_attach_backing(cmd_buf_phys, vqueue_phys, 1, fb_phys, width * height * 4);
self.send_set_scanout(cmd_buf_phys, vqueue_phys, 0, 1, width, height);
}
fn send_cmd(&self, cmd_phys: usize, cmd_len: u32, resp_phys: usize, resp_len: u32, vqueue_phys: usize) {
unsafe {
let descs = vqueue_phys as *mut [u64; 2]; // each desc = addr(u64) + len(u32) + flags(u16) + next(u16)
let desc0 = vqueue_phys as *mut u8;
// desc 0: request (readable)
core::ptr::write_volatile(desc0 as *mut u64, cmd_phys as u64);
core::ptr::write_volatile(desc0.add(8) as *mut u32, cmd_len);
core::ptr::write_volatile(desc0.add(12) as *mut u16, 1); // NEXT
core::ptr::write_volatile(desc0.add(14) as *mut u16, 1); // next=1
// desc 1: response (writable)
let desc1 = desc0.add(16);
core::ptr::write_volatile(desc1 as *mut u64, resp_phys as u64);
core::ptr::write_volatile(desc1.add(8) as *mut u32, resp_len);
core::ptr::write_volatile(desc1.add(12) as *mut u16, 2); // WRITE
core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
// avail ring: after descs (8 descs * 16 bytes = 128 bytes)
let avail = vqueue_phys + QUEUE_SIZE * 16;
let avail_idx = core::ptr::read_volatile((avail + 2) as *const u16);
core::ptr::write_volatile(
(avail + 4 + (avail_idx as usize % QUEUE_SIZE) * 2) as *mut u16,
0,
);
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
core::ptr::write_volatile((avail + 2) as *mut u16, avail_idx.wrapping_add(1));
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
mmio_write(self.base, 0x050, 0); // notify queue 0
// poll used ring (at page boundary = vqueue_phys + 4096)
let used = vqueue_phys + 4096;
let expected = avail_idx.wrapping_add(1);
let mut timeout = 10_000_000u32;
while core::ptr::read_volatile((used + 2) as *const u16) != expected {
core::hint::spin_loop();
timeout -= 1;
if timeout == 0 { return; }
}
}
}
fn send_create_2d(&self, cmd_phys: usize, vq_phys: usize, resource_id: u32, width: u32, height: u32) {
// cmd header (24 bytes) + create_2d fields (16 bytes) = 40 bytes
unsafe {
let p = cmd_phys as *mut u8;
core::ptr::write_bytes(p, 0, 4096);
core::ptr::write_volatile(p as *mut u32, 0x0101); // RESOURCE_CREATE_2D
core::ptr::write_volatile(p.add(24) as *mut u32, resource_id);
core::ptr::write_volatile(p.add(28) as *mut u32, 1); // B8G8R8A8_UNORM
core::ptr::write_volatile(p.add(32) as *mut u32, width);
core::ptr::write_volatile(p.add(36) as *mut u32, height);
}
let resp_phys = cmd_phys + 512;
self.send_cmd(cmd_phys, 40, resp_phys, 24, vq_phys);
}
fn send_attach_backing(&self, cmd_phys: usize, vq_phys: usize, resource_id: u32, fb_phys: usize, fb_size: u32) {
// header (24) + attach_backing (8) + mem_entry (16) = 48 bytes
unsafe {
let p = cmd_phys as *mut u8;
core::ptr::write_bytes(p, 0, 512);
core::ptr::write_volatile(p as *mut u32, 0x0104); // RESOURCE_ATTACH_BACKING
core::ptr::write_volatile(p.add(24) as *mut u32, resource_id);
core::ptr::write_volatile(p.add(28) as *mut u32, 1); // nr_entries
// mem_entry
core::ptr::write_volatile(p.add(32) as *mut u64, fb_phys as u64);
core::ptr::write_volatile(p.add(40) as *mut u32, fb_size);
}
let resp_phys = cmd_phys + 512;
self.send_cmd(cmd_phys, 48, resp_phys, 24, vq_phys);
}
fn send_set_scanout(&self, cmd_phys: usize, vq_phys: usize, scanout_id: u32, resource_id: u32, width: u32, height: u32) {
// header (24) + rect (16) + scanout_id (4) + resource_id (4) = 48 bytes
unsafe {
let p = cmd_phys as *mut u8;
core::ptr::write_bytes(p, 0, 512);
core::ptr::write_volatile(p as *mut u32, 0x0103); // SET_SCANOUT
// rect: x=0, y=0, width, height at offset 24
core::ptr::write_volatile(p.add(32) as *mut u32, width);
core::ptr::write_volatile(p.add(36) as *mut u32, height);
core::ptr::write_volatile(p.add(40) as *mut u32, scanout_id);
core::ptr::write_volatile(p.add(44) as *mut u32, resource_id);
}
let resp_phys = cmd_phys + 512;
self.send_cmd(cmd_phys, 48, resp_phys, 24, vq_phys);
pub fn setup_framebuffer(&self, cmd_phys: usize, vq_phys: usize, fb_phys: usize, width: u32, height: u32) {
let queue = VirtioQueue::new(QueueAddrs::from_base(vq_phys));
let dma = GpuDmaAddrs {
cmd_pa: cmd_phys as u64,
cmd_va: cmd_phys,
resp_pa: (cmd_phys + 512) as u64,
};
gpu::create_2d(&self.mmio, &queue, &dma, 1, width, height);
gpu::attach_backing(&self.mmio, &queue, &dma, 1, fb_phys as u64, width * height * 4);
gpu::set_scanout(&self.mmio, &queue, &dma, 0, 1, width, height);
}
}