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refactor: extract shared hw-virtio crate, eliminate VirtIO protocol duplication

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Two VirtIO block and two VirtIO GPU implementations (adapter + driver)
shared 90% of their protocol logic. Extracted the common code into
hw-virtio, parameterized by MmioAccess trait.

New crate: hw-virtio (no_std, zero deps)
  - mmio.rs: MmioAccess trait, DirectMmio, init_legacy_device(), scan
  - queue.rs: VirtioQueue with descriptor chain submit + poll
  - block.rs: block read protocol (3-descriptor chain)
  - gpu.rs: GPU commands (create_2d, attach_backing, set_scanout,
            transfer_to_host, resource_flush)

Adapter thin wrappers (identity-mapped, statics for DMA):
  - virtio_blk.rs: 220 → 53 lines
  - virtio_gpu.rs: 165 → 37 lines

Driver thin wrappers (mapped VAs, phys-info for DMA):
  - drivers/block/virtio: 139 → 70 lines
  - drivers/framebuffer/virtio: 146 → 95 lines

Also deleted input-server/input_device.rs (1-line re-export,
superseded by port-input-device).
This commit is contained in:
Gabriel Kaszewski
2026-10-18 13:29:28 +02:00
parent 8d53fa9ac5
commit 3a0395453b
21 changed files with 483 additions and 562 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
crates/drivers/framebuffer/virtio/Cargo.toml
View File

@@ -5,3 +5,4 @@ edition = "2024"
[dependencies]
port-framebuffer = { workspace = true }
hw-virtio = { workspace = true }

120
crates/drivers/framebuffer/virtio/src/lib.rs
View File

@@ -1,5 +1,8 @@
#![no_std]
use hw_virtio::mmio::MmioAccess;
use hw_virtio::queue::{QueueAddrs, VirtioQueue};
use hw_virtio::gpu::{self, GpuDmaAddrs};
use port_framebuffer::Framebuffer;
const GPU_MMIO_VA: usize = 0x20000;
@@ -8,13 +11,23 @@ const CMDBUF_VA: usize = 0x23000;
const PHYSINFO_VA: usize = 0x24000;
const FB_VA: usize = 0x100000;
const FB_BPP: usize = 4;
const QUEUE_SIZE: usize = 8;
struct GpuMmio;
impl MmioAccess for GpuMmio {
fn read(&self, offset: usize) -> u32 {
unsafe { core::ptr::read_volatile((GPU_MMIO_VA + offset) as *const u32) }
}
fn write(&self, offset: usize, val: u32) {
unsafe { core::ptr::write_volatile((GPU_MMIO_VA + offset) as *mut u32, val) }
}
}
struct PhysInfo {
cmd_pa: u64,
resp_pa: u64,
width: u64,
height: u64,
width: u16,
height: u16,
}
fn read_phys_info() -> PhysInfo {
@@ -23,95 +36,34 @@ fn read_phys_info() -> PhysInfo {
PhysInfo {
cmd_pa: core::ptr::read_volatile(p),
resp_pa: core::ptr::read_volatile(p.add(1)),
width: core::ptr::read_volatile(p.add(3)),
height: core::ptr::read_volatile(p.add(4)),
width: core::ptr::read_volatile(p.add(3)) as u16,
height: core::ptr::read_volatile(p.add(4)) as u16,
}
}
}
fn mmio_write(offset: usize, val: u32) {
unsafe { core::ptr::write_volatile((GPU_MMIO_VA + offset) as *mut u32, val) }
}
pub struct VirtioFramebuffer {
mmio: GpuMmio,
queue: VirtioQueue,
dma: GpuDmaAddrs,
width: u16,
height: u16,
stride: usize,
phys: PhysInfo,
}
impl VirtioFramebuffer {
pub fn new() -> Self {
let phys = read_phys_info();
let width = phys.width as u16;
let height = phys.height as u16;
let stride = width as usize * FB_BPP;
Self { width, height, stride, phys }
}
fn send_gpu_cmd(&self, cmd_len: u32, resp_len: u32) {
unsafe {
let desc0 = VQUEUE_VA as *mut u8;
core::ptr::write_volatile(desc0 as *mut u64, self.phys.cmd_pa);
core::ptr::write_volatile(desc0.add(8) as *mut u32, cmd_len);
core::ptr::write_volatile(desc0.add(12) as *mut u16, 1);
core::ptr::write_volatile(desc0.add(14) as *mut u16, 1);
let desc1 = desc0.add(16);
core::ptr::write_volatile(desc1 as *mut u64, self.phys.resp_pa);
core::ptr::write_volatile(desc1.add(8) as *mut u32, resp_len);
core::ptr::write_volatile(desc1.add(12) as *mut u16, 2);
core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
let avail = VQUEUE_VA + QUEUE_SIZE * 16;
let avail_idx = core::ptr::read_volatile((avail + 2) as *const u16);
core::ptr::write_volatile(
(avail + 4 + (avail_idx as usize % QUEUE_SIZE) * 2) as *mut u16,
0,
);
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
core::ptr::write_volatile((avail + 2) as *mut u16, avail_idx.wrapping_add(1));
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
mmio_write(0x050, 0);
let used = VQUEUE_VA + 4096;
let expected = avail_idx.wrapping_add(1);
let mut timeout = 10_000_000u32;
while core::ptr::read_volatile((used + 2) as *const u16) != expected {
core::hint::spin_loop();
timeout -= 1;
if timeout == 0 { return; }
}
let stride = phys.width as usize * FB_BPP;
Self {
mmio: GpuMmio,
queue: VirtioQueue::new(QueueAddrs::from_base(VQUEUE_VA)),
dma: GpuDmaAddrs { cmd_pa: phys.cmd_pa, cmd_va: CMDBUF_VA, resp_pa: phys.resp_pa },
width: phys.width,
height: phys.height,
stride,
}
}
fn transfer_and_flush(&self, x: u32, y: u32, w: u32, h: u32) {
unsafe {
let p = CMDBUF_VA as *mut u8;
core::ptr::write_bytes(p, 0, 512);
core::ptr::write_volatile(p as *mut u32, 0x0105);
core::ptr::write_volatile(p.add(24) as *mut u32, x);
core::ptr::write_volatile(p.add(28) as *mut u32, y);
core::ptr::write_volatile(p.add(32) as *mut u32, w);
core::ptr::write_volatile(p.add(36) as *mut u32, h);
core::ptr::write_volatile(p.add(40) as *mut u64, 0);
core::ptr::write_volatile(p.add(48) as *mut u32, 1);
}
self.send_gpu_cmd(56, 24);
unsafe {
let p = CMDBUF_VA as *mut u8;
core::ptr::write_bytes(p, 0, 512);
core::ptr::write_volatile(p as *mut u32, 0x0106);
core::ptr::write_volatile(p.add(24) as *mut u32, x);
core::ptr::write_volatile(p.add(28) as *mut u32, y);
core::ptr::write_volatile(p.add(32) as *mut u32, w);
core::ptr::write_volatile(p.add(36) as *mut u32, h);
core::ptr::write_volatile(p.add(40) as *mut u32, 1);
}
self.send_gpu_cmd(48, 24);
}
}
impl Framebuffer for VirtioFramebuffer {
@@ -125,22 +77,20 @@ impl Framebuffer for VirtioFramebuffer {
}
fn fill_rect(&mut self, x: u16, y: u16, w: u16, h: u16, color: u32) {
for dy in 0..h {
for dx in 0..w {
self.write_pixel(x + dx, y + dy, color);
}
}
for dy in 0..h { for dx in 0..w { self.write_pixel(x + dx, y + dy, color); } }
}
fn clear(&mut self, color: u32) {
let total = self.width as usize * self.height as usize;
let buf = FB_VA as *mut u32;
for i in 0..total {
unsafe { core::ptr::write_volatile(buf.add(i), color); }
unsafe { core::ptr::write_volatile((FB_VA as *mut u32).add(i), color); }
}
}
fn flush(&mut self) {
self.transfer_and_flush(0, 0, self.width as u32, self.height as u32);
let w = self.width as u32;
let h = self.height as u32;
gpu::transfer_to_host(&self.mmio, &self.queue, &self.dma, 1, 0, 0, w, h);
gpu::resource_flush(&self.mmio, &self.queue, &self.dma, 1, 0, 0, w, h);
}
}