refactor: extract ports/drivers/bins layers — clean dependency inversion
Separate abstractions from implementations following DIP:
servers/ drivers/
│ │
▼ ▼
ports/ (trait-only crates, zero deps)
New crates:
ports/ (abstractions):
- port-framebuffer: Framebuffer trait
- port-block-device: BlockDevice trait + SectorId
- port-input-device: InputDevice trait + InputEvent types
drivers/ (implementations depend on ports/):
- driver-framebuffer-virtio: VirtIO GPU framebuffer
- driver-framebuffer-mock: test double
- driver-block-virtio: VirtIO block device
bins/ (composition roots wire server + driver):
- display-qemu: DisplayServer<VirtioFramebuffer>
- storage-qemu: storage server with VirtIO block
Servers no longer own their hardware traits or driver code.
Neither server nor driver depends on the other — both point
inward to the port abstraction.
This commit is contained in:
7
crates/drivers/framebuffer/virtio/Cargo.toml
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7
crates/drivers/framebuffer/virtio/Cargo.toml
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@@ -0,0 +1,7 @@
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[package]
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name = "driver-framebuffer-virtio"
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version = "0.1.0"
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edition = "2024"
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[dependencies]
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port-framebuffer = { workspace = true }
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146
crates/drivers/framebuffer/virtio/src/lib.rs
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146
crates/drivers/framebuffer/virtio/src/lib.rs
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@@ -0,0 +1,146 @@
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#![no_std]
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use port_framebuffer::Framebuffer;
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const GPU_MMIO_VA: usize = 0x20000;
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const VQUEUE_VA: usize = 0x21000;
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const CMDBUF_VA: usize = 0x23000;
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const PHYSINFO_VA: usize = 0x24000;
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const FB_VA: usize = 0x100000;
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const FB_BPP: usize = 4;
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const QUEUE_SIZE: usize = 8;
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struct PhysInfo {
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cmd_pa: u64,
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resp_pa: u64,
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width: u64,
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height: u64,
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}
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fn read_phys_info() -> PhysInfo {
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unsafe {
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let p = PHYSINFO_VA as *const u64;
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PhysInfo {
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cmd_pa: core::ptr::read_volatile(p),
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resp_pa: core::ptr::read_volatile(p.add(1)),
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width: core::ptr::read_volatile(p.add(3)),
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height: core::ptr::read_volatile(p.add(4)),
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}
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}
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}
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fn mmio_write(offset: usize, val: u32) {
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unsafe { core::ptr::write_volatile((GPU_MMIO_VA + offset) as *mut u32, val) }
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}
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pub struct VirtioFramebuffer {
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width: u16,
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height: u16,
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stride: usize,
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phys: PhysInfo,
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}
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impl VirtioFramebuffer {
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pub fn new() -> Self {
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let phys = read_phys_info();
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let width = phys.width as u16;
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let height = phys.height as u16;
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let stride = width as usize * FB_BPP;
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Self { width, height, stride, phys }
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}
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fn send_gpu_cmd(&self, cmd_len: u32, resp_len: u32) {
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unsafe {
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let desc0 = VQUEUE_VA as *mut u8;
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core::ptr::write_volatile(desc0 as *mut u64, self.phys.cmd_pa);
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core::ptr::write_volatile(desc0.add(8) as *mut u32, cmd_len);
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core::ptr::write_volatile(desc0.add(12) as *mut u16, 1);
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core::ptr::write_volatile(desc0.add(14) as *mut u16, 1);
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let desc1 = desc0.add(16);
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core::ptr::write_volatile(desc1 as *mut u64, self.phys.resp_pa);
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core::ptr::write_volatile(desc1.add(8) as *mut u32, resp_len);
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core::ptr::write_volatile(desc1.add(12) as *mut u16, 2);
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core::ptr::write_volatile(desc1.add(14) as *mut u16, 0);
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let avail = VQUEUE_VA + QUEUE_SIZE * 16;
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let avail_idx = core::ptr::read_volatile((avail + 2) as *const u16);
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core::ptr::write_volatile(
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(avail + 4 + (avail_idx as usize % QUEUE_SIZE) * 2) as *mut u16,
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0,
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);
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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core::ptr::write_volatile((avail + 2) as *mut u16, avail_idx.wrapping_add(1));
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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mmio_write(0x050, 0);
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let used = VQUEUE_VA + 4096;
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let expected = avail_idx.wrapping_add(1);
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let mut timeout = 10_000_000u32;
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while core::ptr::read_volatile((used + 2) as *const u16) != expected {
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core::hint::spin_loop();
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timeout -= 1;
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if timeout == 0 { return; }
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}
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}
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}
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fn transfer_and_flush(&self, x: u32, y: u32, w: u32, h: u32) {
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unsafe {
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let p = CMDBUF_VA as *mut u8;
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core::ptr::write_bytes(p, 0, 512);
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core::ptr::write_volatile(p as *mut u32, 0x0105);
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core::ptr::write_volatile(p.add(24) as *mut u32, x);
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core::ptr::write_volatile(p.add(28) as *mut u32, y);
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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core::ptr::write_volatile(p.add(40) as *mut u64, 0);
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core::ptr::write_volatile(p.add(48) as *mut u32, 1);
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}
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self.send_gpu_cmd(56, 24);
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unsafe {
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let p = CMDBUF_VA as *mut u8;
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core::ptr::write_bytes(p, 0, 512);
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core::ptr::write_volatile(p as *mut u32, 0x0106);
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core::ptr::write_volatile(p.add(24) as *mut u32, x);
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core::ptr::write_volatile(p.add(28) as *mut u32, y);
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core::ptr::write_volatile(p.add(32) as *mut u32, w);
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core::ptr::write_volatile(p.add(36) as *mut u32, h);
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core::ptr::write_volatile(p.add(40) as *mut u32, 1);
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}
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self.send_gpu_cmd(48, 24);
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}
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}
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impl Framebuffer for VirtioFramebuffer {
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fn width(&self) -> u16 { self.width }
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fn height(&self) -> u16 { self.height }
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fn write_pixel(&mut self, x: u16, y: u16, color: u32) {
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if x >= self.width || y >= self.height { return; }
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let offset = (y as usize) * self.stride + (x as usize) * FB_BPP;
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unsafe { core::ptr::write_volatile((FB_VA + offset) as *mut u32, color); }
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}
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fn fill_rect(&mut self, x: u16, y: u16, w: u16, h: u16, color: u32) {
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for dy in 0..h {
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for dx in 0..w {
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self.write_pixel(x + dx, y + dy, color);
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}
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}
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}
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fn clear(&mut self, color: u32) {
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let total = self.width as usize * self.height as usize;
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let buf = FB_VA as *mut u32;
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for i in 0..total {
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unsafe { core::ptr::write_volatile(buf.add(i), color); }
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}
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}
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fn flush(&mut self) {
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self.transfer_and_flush(0, 0, self.width as u32, self.height as u32);
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}
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}
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