feat(adapter-riscv): add trap handling, timer via SBI, and S/U-mode trap vector

2026-10-18 01:53:37 +02:00
parent d9de828420
commit 941704bbbc
3 changed files with 237 additions and 0 deletions
--- a/crates/adapter-riscv/src/main.rs
+++ b/crates/adapter-riscv/src/main.rs
@@ -2,6 +2,8 @@
 #![no_main]

 mod page_table;
+mod timer;
+mod trap;
 mod uart;

 use core::arch::global_asm;
@@ -48,6 +50,10 @@ extern "C" fn kmain() -> ! {
    page_table::activate(kernel_pt);
    uart.write_str("k-os: MMU enabled (Sv39)\n");

+    trap::init_trap();
+    timer::init_timer();
+    uart.write_str("k-os: traps and timer initialized\n");
+
    loop {
        unsafe { core::arch::asm!("wfi") };
    }