7724a5bd0a
feat: implement context switching, SavedContext with pc/status fields, wire all syscall outcomes and timer preemption
2026-10-18 02:34:36 +02:00
5a45c14cf5
feat(adapter-riscv): replace static mut with KernelCell, complete all 17 syscall decoders, wire timer and PLIC interrupts to kernel
2026-10-18 02:29:46 +02:00
570fe22bee
feat: userspace round-trip — syscall stubs, ecall dispatch, U-mode entry and exit on QEMU
2026-10-18 02:15:35 +02:00
d327794d33
refactor(adapter-riscv): restructure into hw/, mmu/, trap/ modules with board constants
...
Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate.
All QEMU virt addresses consolidated in board.rs.
Structure mirrors future adapter-arm/ layout.
2026-10-18 02:05:57 +02:00
66a730b2fe
feat(adapter-riscv): IPC demo — two processes exchange a message on QEMU virt
2026-10-18 01:58:18 +02:00
2436061215
feat(adapter-riscv): add RiscVPlatform, PLIC driver, and kernel boot on QEMU
2026-10-18 01:56:18 +02:00
941704bbbc
feat(adapter-riscv): add trap handling, timer via SBI, and S/U-mode trap vector
2026-10-18 01:53:37 +02:00
d9de828420
feat(adapter-riscv): add Sv39 page tables with identity mapping and MMU activation
2026-10-18 01:48:00 +02:00
44a0ead7f2
feat(adapter-riscv): boot on QEMU virt with UART hello world
2026-10-18 01:46:47 +02:00
