Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate. All QEMU virt addresses consolidated in board.rs. Structure mirrors future adapter-arm/ layout.
70 lines
1.6 KiB
Rust
70 lines
1.6 KiB
Rust
use domain::memory::MemoryRegion;
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use domain::thread::SavedContext;
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use platform::Platform;
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use types::{
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address::{EntryPoint, PhysicalAddress, StackPointer},
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bounded::PageCount,
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id::{CoreId, IrqId, ProcessId},
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permission::PermissionSet,
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time::{Ticks, TimerDuration},
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};
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use crate::board;
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use crate::hw::{plic::Plic, timer};
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pub struct RiscVPlatform {
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num_cores: u8,
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}
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impl RiscVPlatform {
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pub fn new() -> Self {
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Self { num_cores: 1 }
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}
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}
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impl Platform for RiscVPlatform {
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fn configure_protection(&mut self, _process: ProcessId, _regions: &[MemoryRegion]) {}
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fn context_switch(&mut self, _from: &mut SavedContext, _to: &SavedContext) {}
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fn enable_user_mode(&mut self, _entry: EntryPoint, _stack: StackPointer) -> ! {
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loop { unsafe { core::arch::asm!("wfi") }; }
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}
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fn set_timer(&mut self, _duration: TimerDuration) {
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let now = timer::read_time();
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timer::set_next(now + board::TICK_INTERVAL);
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}
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fn current_ticks(&self) -> Ticks {
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Ticks::from_raw(timer::read_time())
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}
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fn mask_irq(&mut self, irq: IrqId) {
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Plic::disable(irq.raw() as u32);
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}
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fn unmask_irq(&mut self, irq: IrqId) {
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Plic::enable(irq.raw() as u32);
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}
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fn send_ipi(&mut self, _target: CoreId) {}
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fn core_id(&self) -> CoreId {
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CoreId::from_raw(0)
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}
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fn num_cores(&self) -> u8 {
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self.num_cores
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}
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fn map_shared(
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&mut self,
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_process: ProcessId,
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_base: PhysicalAddress,
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_size: PageCount,
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_permissions: PermissionSet,
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) {
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}
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}
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