Files
k-os/crates/adapter-riscv/src/platform.rs
Gabriel Kaszewski d327794d33 refactor(adapter-riscv): restructure into hw/, mmu/, trap/ modules with board constants
Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate.
All QEMU virt addresses consolidated in board.rs.
Structure mirrors future adapter-arm/ layout.
2026-10-18 02:05:57 +02:00

70 lines
1.6 KiB
Rust

use domain::memory::MemoryRegion;
use domain::thread::SavedContext;
use platform::Platform;
use types::{
address::{EntryPoint, PhysicalAddress, StackPointer},
bounded::PageCount,
id::{CoreId, IrqId, ProcessId},
permission::PermissionSet,
time::{Ticks, TimerDuration},
};
use crate::board;
use crate::hw::{plic::Plic, timer};
pub struct RiscVPlatform {
num_cores: u8,
}
impl RiscVPlatform {
pub fn new() -> Self {
Self { num_cores: 1 }
}
}
impl Platform for RiscVPlatform {
fn configure_protection(&mut self, _process: ProcessId, _regions: &[MemoryRegion]) {}
fn context_switch(&mut self, _from: &mut SavedContext, _to: &SavedContext) {}
fn enable_user_mode(&mut self, _entry: EntryPoint, _stack: StackPointer) -> ! {
loop { unsafe { core::arch::asm!("wfi") }; }
}
fn set_timer(&mut self, _duration: TimerDuration) {
let now = timer::read_time();
timer::set_next(now + board::TICK_INTERVAL);
}
fn current_ticks(&self) -> Ticks {
Ticks::from_raw(timer::read_time())
}
fn mask_irq(&mut self, irq: IrqId) {
Plic::disable(irq.raw() as u32);
}
fn unmask_irq(&mut self, irq: IrqId) {
Plic::enable(irq.raw() as u32);
}
fn send_ipi(&mut self, _target: CoreId) {}
fn core_id(&self) -> CoreId {
CoreId::from_raw(0)
}
fn num_cores(&self) -> u8 {
self.num_cores
}
fn map_shared(
&mut self,
_process: ProcessId,
_base: PhysicalAddress,
_size: PageCount,
_permissions: PermissionSet,
) {
}
}