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refactor(adapter-riscv): restructure into hw/, mmu/, trap/ modules with board constants

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Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate.
All QEMU virt addresses consolidated in board.rs.
Structure mirrors future adapter-arm/ layout.
This commit is contained in:
Gabriel Kaszewski
2026-10-18 02:05:57 +02:00
parent 66a730b2fe
commit d327794d33
13 changed files with 100 additions and 109 deletions
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8
crates/adapter-riscv/src/board.rs Normal file
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pub const RAM_BASE: usize = 0x80000000;
pub const RAM_SIZE: usize = 128 * 1024 * 1024;
pub const UART_BASE: usize = 0x10000000;
pub const PLIC_BASE: usize = 0x0C000000;
pub const CLINT_BASE: usize = 0x02000000;
pub const USER_POOL_BASE: usize = 0x84000000;
pub const USER_POOL_PAGES: usize = 256;
pub const TICK_INTERVAL: u64 = 10_000_000;