refactor(adapter-riscv): restructure into hw/, mmu/, trap/ modules with board constants

Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate.
All QEMU virt addresses consolidated in board.rs.
Structure mirrors future adapter-arm/ layout.

crates/adapter-riscv/src/hw/plic.rs

@@ -0,0 +1,44 @@
+use crate::board;
+
+const PLIC_PRIORITY: usize = board::PLIC_BASE;
+const PLIC_S_ENABLE: usize = board::PLIC_BASE + 0x2080;
+const PLIC_S_THRESHOLD: usize = board::PLIC_BASE + 0x201000;
+const PLIC_S_CLAIM: usize = board::PLIC_BASE + 0x201004;
+
+pub struct Plic;
+
+impl Plic {
+    pub fn init() {
+        unsafe { core::ptr::write_volatile(PLIC_S_THRESHOLD as *mut u32, 0) };
+    }
+
+    pub fn enable(irq: u32) {
+        let word = (irq / 32) as usize;
+        let bit = irq % 32;
+        let addr = PLIC_S_ENABLE + word * 4;
+        unsafe {
+            let current = core::ptr::read_volatile(addr as *const u32);
+            core::ptr::write_volatile(addr as *mut u32, current | (1 << bit));
+        }
+        let prio_addr = PLIC_PRIORITY + (irq as usize) * 4;
+        unsafe { core::ptr::write_volatile(prio_addr as *mut u32, 1) };
+    }
+
+    pub fn disable(irq: u32) {
+        let word = (irq / 32) as usize;
+        let bit = irq % 32;
+        let addr = PLIC_S_ENABLE + word * 4;
+        unsafe {
+            let current = core::ptr::read_volatile(addr as *const u32);
+            core::ptr::write_volatile(addr as *mut u32, current & !(1 << bit));
+        }
+    }
+
+    pub fn claim() -> u32 {
+        unsafe { core::ptr::read_volatile(PLIC_S_CLAIM as *const u32) }
+    }
+
+    pub fn complete(irq: u32) {
+        unsafe { core::ptr::write_volatile(PLIC_S_CLAIM as *mut u32, irq) };
+    }
+}