refactor(adapter-riscv): restructure into hw/, mmu/, trap/ modules with board constants

Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate.
All QEMU virt addresses consolidated in board.rs.
Structure mirrors future adapter-arm/ layout.

crates/adapter-riscv/src/hw/uart.rs

@@ -0,0 +1,60 @@
+use crate::board;
+
+pub struct Uart {
+    base: usize,
+}
+
+impl Uart {
+    pub fn new() -> Self {
+        Self { base: board::UART_BASE }
+    }
+
+    pub fn put_char(&self, byte: u8) {
+        let ptr = self.base as *mut u8;
+        unsafe { core::ptr::write_volatile(ptr, byte) };
+    }
+
+    pub fn write_str(&self, s: &str) {
+        for byte in s.bytes() {
+            self.put_char(byte);
+        }
+    }
+
+    pub fn write_hex(&self, mut value: usize) {
+        self.write_str("0x");
+        if value == 0 {
+            self.put_char(b'0');
+            return;
+        }
+        let mut buf = [0u8; 16];
+        let mut i = 0;
+        while value > 0 {
+            let digit = (value & 0xF) as u8;
+            buf[i] = if digit < 10 { b'0' + digit } else { b'a' + digit - 10 };
+            value >>= 4;
+            i += 1;
+        }
+        while i > 0 {
+            i -= 1;
+            self.put_char(buf[i]);
+        }
+    }
+
+    pub fn write_dec(&self, mut value: usize) {
+        if value == 0 {
+            self.put_char(b'0');
+            return;
+        }
+        let mut buf = [0u8; 20];
+        let mut i = 0;
+        while value > 0 {
+            buf[i] = b'0' + (value % 10) as u8;
+            value /= 10;
+            i += 1;
+        }
+        while i > 0 {
+            i -= 1;
+            self.put_char(buf[i]);
+        }
+    }
+}