refactor(adapter-riscv): restructure into hw/, mmu/, trap/ modules with board constants

Add Priority::DEFAULT and TimeSlice::DEFAULT to types crate.
All QEMU virt addresses consolidated in board.rs.
Structure mirrors future adapter-arm/ layout.

crates/adapter-riscv/src/platform.rs

@@ -9,8 +9,8 @@ use types::{
     time::{Ticks, TimerDuration},
 };
 
-use crate::plic::Plic;
-use crate::timer;
+use crate::board;
+use crate::hw::{plic::Plic, timer};
 
 pub struct RiscVPlatform {
     num_cores: u8,
@@ -23,22 +23,17 @@ impl RiscVPlatform {
 }
 
 impl Platform for RiscVPlatform {
-    fn configure_protection(&mut self, _process: ProcessId, _regions: &[MemoryRegion]) {
-        // page table activation happens separately per context switch
-    }
+    fn configure_protection(&mut self, _process: ProcessId, _regions: &[MemoryRegion]) {}
 
-    fn context_switch(&mut self, _from: &mut SavedContext, _to: &SavedContext) {
-        // context switch is handled by the trap vector assembly
-    }
+    fn context_switch(&mut self, _from: &mut SavedContext, _to: &SavedContext) {}
 
     fn enable_user_mode(&mut self, _entry: EntryPoint, _stack: StackPointer) -> ! {
-        // handled by setting up TrapFrame and sret in the main loop
         loop { unsafe { core::arch::asm!("wfi") }; }
     }
 
     fn set_timer(&mut self, _duration: TimerDuration) {
         let now = timer::read_time();
-        timer::set_next_timer(now + 10_000_000);
+        timer::set_next(now + board::TICK_INTERVAL);
     }
 
     fn current_ticks(&self) -> Ticks {
@@ -53,9 +48,7 @@ impl Platform for RiscVPlatform {
         Plic::enable(irq.raw() as u32);
     }
 
-    fn send_ipi(&mut self, _target: CoreId) {
-        // single core — no-op
-    }
+    fn send_ipi(&mut self, _target: CoreId) {}
 
     fn core_id(&self) -> CoreId {
         CoreId::from_raw(0)
@@ -72,6 +65,5 @@ impl Platform for RiscVPlatform {
         _size: PageCount,
         _permissions: PermissionSet,
     ) {
-        // page table mapping for shared memory — deferred to full MMU integration
     }
 }